HD64F2149YV datasheet(660/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 632 of 1044

REJ09B0280-0300

SIRQCR1 Bit 2—HIRQ10 Interrupt Enable 2 (IRQ10E2): Enables or disables a HIRQ10

interrupt request when OBF2 is set by an ODR2 write.

Bit 2

IRQ10E2

Description

HIRQ10 interrupt request by OBF2 and IRQ10E2 is disabled

(Initial value)

[Clearing conditions]

• Writing 0 to IRQ10E2

• LPC hardware reset, LPC software reset

• Clearing OBF2 to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ10 interrupt request by setting OBF2 to 1 is enabled

[When IEDIR = 1]

HIRQ10 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ10E2 = 0

SIRQCR1 Bit 1—HIRQ9 Interrupt Enable 2 (IRQ9E2): Enables or disables a HIRQ9 interrupt

request when OBF2 is set by an ODR2 write.

Bit 1

IRQ9E2

Description

HIRQ9 interrupt request by OBF2 and IRQ9E2 is disabled

(Initial value)

[Clearing conditions]

• Writing 0 to IRQ9E2

• LPC hardware reset, LPC software reset

• Clearing OBF2 to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ9 interrupt request by setting OBF2 to 1 is enabled

[When IEDIR = 1]

HIRQ9 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ9E2 = 0

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