HD64F2149YV datasheet(661/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 633 of 1044

REJ09B0280-0300

SIRQCR1 Bit 0—HIRQ6 Interrupt Enable 2 (IRQ6E2): Enables or disables a HIRQ6 interrupt

request when OBF2 is set by an ODR2 write.

Bit 0

IRQ6E2

Description

HIRQ6 interrupt request by OBF2 and IRQ6E2 is disabled

(Initial value)

[Clearing conditions]

• Writing 0 to IRQ6E2

• LPC hardware reset, LPC software reset

• Clearing OBF2 to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ6 interrupt request by setting OBF2 to 1 is enabled

[When IEDIR = 1]

HIRQ6 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ6E2 = 0

SIRQCR0 Bit 1—HIRQ12 Interrupt Enable 1 (IRQ12E1): Enables or disables a HIRQ12

interrupt request when OBF1 is set by an ODR1 write.

Bit 1

IRQ12E1

Description

HIRQ12 interrupt request by OBF1 and IRQ12E1 is disabled

(Initial value)

[Clearing conditions]

• Writing 0 to IRQ12E1

• LPC hardware reset, LPC software reset

• Clearing OBF1 to 0

HIRQ12 interrupt request by setting OBF1 to 1 is enabled

[Setting condition]

• Writing 1 after reading IRQ12E1 = 0

HD64F2149YV Folha de dados(PDF) 661 Page - Renesas Technology Corp