HD64F2149YV datasheet(61/1075 Pages) RENESAS

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Section 2 CPU

Rev. 3.00 Jan 18, 2006 page 33 of 1044

REJ09B0280-0300

Section 2 CPU

2.1

Overview

The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that

is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit

general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is

ideal for realtime control.

2.1.1

Features

The H8S/2000 CPU has the following features.

• Upward-compatible with H8/300 and H8/300H CPUs

 Can execute H8/300 and H8/300H object programs

• General-register architecture

 Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit

registers)

• Sixty-five basic instructions

 8/16/32-bit arithmetic and logic instructions

 Multiply and divide instructions

 Powerful bit-manipulation instructions

• Eight addressing modes

 Register direct [Rn]

 Register indirect [@ERn]

 Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]

 Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]

 Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]

 Immediate [#xx:8, #xx:16, or #xx:32]

 Program-counter relative [@(d:8,PC) or @(d:16,PC)]

 Memory indirect [@@aa:8]

• 16-Mbyte address space

 Program: 16 Mbytes

 Data:

16 Mbytes (4 Gbytes architecturally)

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