HD64F2149YV datasheet(651/1075 Pages) RENESAS

651 / 1075 page

Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 623 of 1044

REJ09B0280-0300

The initial values of TWR0 to TWR15 after a reset and in standby mode are undetermined.

18B.2.8 Status Registers (STR1 to STR3)

• STR1

Bit

543

210

DBU17

DBU16

DBU15

DBU14

DBU12

IBF1

OBF1

Initial value

000

Slave Read/Write

R/W

R/(W)*

Host Read/Write

RRR

Note:

Only 0 can be written, to clear the flag.

• STR2

Bit

543

210

DBU27

DBU26

DBU25

DBU24

DBU22

IBF2

OBF2

Initial value

000

Slave Read/Write

R/W

R/(W)*

Host Read/Write

RRR

Note:

Only 0 can be written, to clear the flag.

• STR3

Bit

543

210

IBF3B

OBF3B

MWMF

SWMF

DBU32

IBF3A

OBF3

Initial value

000

Slave Read/Write

R/(W)*

RR/(W)*

R/W

R/(W)*

Host Read/Write

RRR

Note:

Only 0 can be written, to clear the flag.

The STR registers are 8-bit registers that indicate status information during host interface

processing. Bits 3, 1, and 0 of STR1 to STR3, and bits 7 to 4 of STR3, are read-only bits to both

the host processor and the slave processor. However, 0 only can be written from the slave

processor to bit 0 of STR1 to STR3, and bits 6 and 4 of STR3, in order to clear the flags to 0. The

registers selected from the host processor according to the I/O address are shown in the following

HD64F2149YV Folha de dados(PDF) 651 Page - Renesas Technology Corp

HD64F2149YV Folha de dados(HTML) 651 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL