HD64F2149YV datasheet(653/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 625 of 1044

REJ09B0280-0300

STR1 to STR3 Bit 0—Output Buffer Full (OBF1, OBF2, OBF3A): Set to 1 when the slave

processor writes to ODR. Cleared to 0 when the host processor reads ODR.

Bit 0

OBF

Description

[Clearing condition]

(Initial value)

When the host processor reads ODR using I/O read cycle, or the slave

processor writes 0 in the OBF bit

[Setting condition]

When the slave processor writes to ODR

STR3 Bit 7—Two-Way Register Input Buffer Full (IBF3B): Set to 1 when the host processor

writes to TWR15. This is an internal interrupt source to the slave processor. IBF3B is cleared to 0

when the slave processor reads TWR15.

Bit 7

IBF3B

Description

[Clearing condition]

(Initial value)

When the slave processor reads TWR15

[Setting condition]

When the host processor writes to TWR15 using I/O write cycle

STR3 Bit 6—Two-Way Register Output Buffer Full (OBF3B): Set to 1 when the slave

processor writes to TWR15. OBF3B is cleared to 0 when the host processor reads TWR15.

Bit 6

OBF3B

Description

[Clearing condition]

(Initial value)

When the host processor reads TWR15 using I/O read cycle, or the slave

processor writes 0 in the OBF3B bit

[Setting condition]

When the slave processor writes to TWR15

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