HD64F2149YV datasheet(652/1075 Pages) RENESAS

652 / 1075 page

Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 624 of 1044

REJ09B0280-0300

table. For information on STR3 selection, see section 18B.2.4, LPC Channel 3 Address Register

(LADR3). In an LPC I/O read cycle, the data in the selected register is transferred to the host

processor.

The STR registers are initialized to H'00 by a reset and in standby mode.

I/O Address

Transfer

Bits 15 to 4

Bit 3

Bit 2

Bit 1

Bit 0

Cycle

Host Register Selection

0000 0000 0110

I/O read

STR1 read

0000 0000 0110

I/O read

STR2 read

STR1, STR2 Bits 7 to 4 and 2—Defined by User (DBU17 to DBU14, DBU12; DBU27 to

DBU24, DBU22)

STR3 Bit 2— Defined by User (DBU32)

The user can use these bits as necessary.

STR1 to STR3 Bit 3—Command/Data (C/

D1 to C/D

D3): When the host processor writes to an

IDR register, bit 2 of the I/O address is written into this bit to indicate whether IDR contains data

or a command.

Bit 3

Description

Contents of data register (IDR) are data

(Initial value)

Contents of data register (IDR) are a command

STR1 to STR3 Bit 1—Input Buffer Full (IBF1 to IBF3A): Set to 1 when the host processor

writes to IDR. This bit is an internal interrupt source to the slave processor. IBF is cleared to 0

when the slave processor reads IDR.

The IBF1 flag setting and clearing conditions are diffrent when the fast A20 gate is used. For

details see table 18B.4.

Bit 1

IBF

Description

[Clearing condition]

(Initial value)

When the slave processor reads IDR

[Setting condition]

When the host processor writes to IDR using I/O write cycle

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