HD64F2149YV datasheet(648/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 620 of 1044

REJ09B0280-0300

I/O Address

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Transfer

Cycle

Host Register Selection

Bit 4

Bit 3

Bit 1

I/O write

IDR3 write, C/

D3 ← 0

Bit 4

Bit 3

Bit 1

I/O write

IDR3 write, C/

D3 ← 1

Bit 4

Bit 3

Bit 1

I/O read

ODR3 read

Bit 4

Bit 3

Bit 1

I/O read

STR3 read

Bit 4

I/O write

TWR0MW write

Bit 4

I/O write

TWR1 to TWR15 write

•

111

Bit 4

I/O read

TWR0SW read

Bit 4

I/O read

TWR1 to TWR15 read

•

111

LADR3L Bit 2—Reserved: This is a readable/writable reserved bit.

LADR3L Bit 0—Two-Way Register Enable (TWRE): Enables or disables two-way register

operation.

LADR3L

Bit 0

TWRE

Description

TWR operation is disabled

(Initial value)

TWR-related I/O address match determination is halted

TWR operation is enabled

18B.2.5 Input Data Registers (IDR1 to IDR3)

Bit

543

210

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Initial value

—

———

Slave Read/Write

Host Read/Write

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