HD64F2149YV datasheet(649/1075 Pages) RENESAS

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 621 of 1044

REJ09B0280-0300

The IDR registers are 8-bit read-only registers to the slave processor, and 8-bit write-only registers

to the host processor. The registers selected from the host according to the I/O address are shown

in the following table. For information on IDR3 selection, see section 18B.2.4, LPC Channel 3

Address Register (LADR3). Data transferred in an LPC I/O write cycle is written to the selected

D bit in STR, to indicate whether

the written information is a command or data.

The initial values of the IDR registers after a reset and in standby mode are undetermined.

I/O Address

Bits 15 to 4

Bit 3

Bit 2

Bit 1

Bit 0

Transfer

Cycle

Host Register Selection

0000 0000 0110

I/O write

IDR1 write, C/

D1 ← 0

0000 0000 0110

I/O write

IDR1 write, C/

D1 ← 1

0000 0000 0110

I/O write

IDR2 write, C/

D2 ← 0

0000 0000 0110

I/O write

IDR2 write, C/

D2 ← 1

18B.2.6 Output Data Registers (ODR1 to ODR3)

Bit

543

210

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Initial value

—

———

Slave Read/Write

R/W

Host Read/Write

RRR

The ODR registers are 8-bit readable/writable registers to the slave processor, and 8-bit read-only

registers to the host processor. The registers selected from the host according to the I/O address

are shown in the following table. For information on ODR3 selection, see section 18B.2.4, LPC

Channel 3 Address Register (LADR3). In an LPC I/O read cycle, the data in the selected register

is transferred to the host.

The initial values of the ODR registers after a reset and in standby mode are undetermined.

I/O Address

Bits 15 to 4

Bit 3

Bit 2

Bit 1

Bit 0

Transfer

Cycle

Host Register Selection

0000 0000 0110

I/O read

ODR1 read

0000 0000 0110

I/O read

ODR2 read

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