ADIN2111BCPZ-R7 datasheet(22/129 Pages) AD

22 / 129 page

Data Sheet

ADIN2111

THEORY OF OPERATION

analog.com

Rev. A | 22 of 129

POWER-DOWN MODES

The ADIN2111 supports the following two power-down modes:

►

Hardware power-down

►

Software power-down

Hardware Power-Down Mode

The hardware power-down mode can be used when no operation is

required on the ADIN2111 and the power consumption needs to be

minimized.

The device enters hardware power-down mode when the RESET

pin is asserted and held low. In this mode, all analog and digital

circuits are disabled, the clocks are gated off, and all the I/O pins

are held in tristate mode.

In this mode, the ADIN2111 power consumption is equivalent to the

internal circuit leakage. The internal registers are not accessible in

this mode.

Software Power-Down Mode

Software power-down mode can be used on each PHY to configure

the ADIN2111 registers before bringing a link up. In this mode, the

PHY 1 (respectively PHY 2) analog and digital circuits are in a low

power state, and the PLL is active and can provide output clocks if

configured to do so. Any signals exposed to the MDI pins, P1_TXP

and P1_TXN (respectively P2_TXP, P2_TXN), are ignored and any

active link on the respective PHY is dropped. The SPI registers are

accessible, and the device can be configured using software.

The PHY 1 (respectively PHY 2) can be configured to automati-

cally enter software power-down mode after power-up, hardware

reset, or software reset using the P1_SWPD_EN (respectively

P2_SWPD_EN) hardware configuration pin signal. The ADIN2111

can also be instructed to enter software power-down mode by set-

ting the software power-down bit (CRSM_SFT_PD) in the software

power-down control register (CRSM_SFT_PD_CNTRL) within the

respective PHY.

The software power-down status bit (CRSM_SFT_PD_RDY) in the

system status register (CRSM_STAT) indicates that the respective

PHY is in software power-down mode.

The ADIN2111 PHY 1 (respectively PHY 2) exits software power-

down mode when the CRSM_SFT_PD bit is cleared within the

respective PHY. After exiting software power-down, and if autone-

gotiation is completed, the PHY 1 (respectively PHY 2) attempts to

bring a link up.

Note that it is necessary to bring PHY 1 out of software power-down

mode to establish a link on PHY 2.

ADIN2111BCPZ-R7 Folha de dados(PDF) 22 Page - Analog Devices

ADIN2111BCPZ-R7 Folha de dados(HTML) 22 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Folha de dados Download

Ligação URL