ADIN2111BCPZ-R7 datasheet(62/129 Pages) AD

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Data Sheet

ADIN2111

REGISTERS

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Rev. A | 62 of 129

Table 53. Bit Descriptions for STATUS1 (Continued)

Bits

Bit Name

Description

Reset

Access

RX_ECC_ERR

ECC Error on Reading the Frame Size from an Rx FIFO. An uncorrectable ECC error was detected

on a reading the frame size field from an Rx FIFO. The FIFO is automatically cleared and the frame

associated with the ECC error and other frames in the Rx FIFO is not lost/dropped.

0x0

R/W1C

SPI_ERR

Detected an Error on an SPI Transaction. When using the generic SPI protocol, this field indicates that a

CRC error was detected. This field is not used with the OPEN Alliance Protocol. See HDRE and CDPE in

STATUS0 for OPEN Alliance SPI errors.

0x0

R/W1C

RESERVED

Reserved.

0x0

R/W1C

P1_RX_IFG_ERR

Rx MAC Interframe Gap Error. If the IFG is too short, the frame is dropped on receive. The threshold

used for measuring the IFG on receive can be set in the P1_RX_IFG register.

0x0

R/W1C

[7:6]

RESERVED

Reserved.

0x0

P1_RX_RDY_HI

Port 1 Rx Ready High Priority. Indicates that there is a high priority frame available on Port 1. When

using the generic SPI protocol, this field can be used on LES to determine which port's receive

FIFO is read next in the case where frames are available on both ports. If P1_RX_RDY_HI is 1 and

P2_RX_RDY_HI is 0, the next frame is read from Port 1 because Port 1 has a high priority frame. If

P1_RX_RDY_HI is 0 and P2_RX_RDY_HI is 1, the next frame is read from Port 2 because Port 2 has a

high priority frame. This field does not drive the interrupt pin. This field is only used with the generic SPI

protocol on LES.

0x0

P1_RX_RDY

Port 1 Rx FIFO Contains Data. In store and forward mode, this field indicates that there is one or

more frames in Port 1 Rx FIFO. In cut through mode, this field indicates that the receive threshold

(RX_THRESH) is reached or the EOF byte of a frame is received. If there are frames in both the Rx high

and low priority FIFOs, the frame from the high priority FIFO is read first by default. This field is only used

with the generic SPI protocol.

0x0

TX_RDY

Tx Ready. If TX_RDY_ON_EMPTY is 0, TX_RDY asserts when frame transmission completes. If

TX_RDY_ON_EMPTY is 1, TX_RDY asserts when the Tx FIFO is empty and frame transmission

completes. This bit is cleared by writing 1 to this field. This field is only used with the generic SPI

protocol.

0x0

R/W1C

[2:0]

RESERVED

Reserved.

0x0

Buffer Status Register

Address: 0x0B, Reset: 0x00003B00, Name: BUFSTS

Table 54. Bit Descriptions for BUFSTS

Bits

Bit Name

Description

Reset

Access

[31:16]

RESERVED

Reserved.

0x0

[15:8]

TXC

Transmit Credits Available. Number of chunk buffers of transmit data currently available for the SPI host to write.

Reading this field allows the SPI host to queue up the number of transmit chunks available into a single DMA,

if desired. The value in this field is saturated to 31 and sent in the 5-bit TXC field of every RX data footer. The

default (maximum) number of transmit buffer credits available is implementation specific. This field is only used

with the OPEN Alliance SPI protocol.

0x3B

[7:0]

RCA

Receive Chunks Available. Number of chunks of receive data currently available for the SPI host to read.

Reading this field allows the SPI host to queue up the number of receive chunks available into a single DMA, if

desired. This field is only used with the OPEN Alliance SPI protocol.

0x0

Interrupt Mask Register 0

Address: 0x0C, Reset: 0x00001FBF, Name: IMASK0

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