ADIN2111BCPZ-R7 datasheet(50/129 Pages) AD

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Data Sheet

ADIN2111

SWITCH SPI

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Rev. A | 50 of 129

operation of the ADIN2111 to be configured without having to write

to it over the SPI.

Recommended Register Operation

Many of the PHY registers in the ADIN2111 are defined in the IEEE

Standard 802.3, and the exact behavior of these registers follows

the standard. This behavior is not always obvious and is described

in this section, in addition to the recommended operation and use of

the registers.

Latch Low Registers

The IEEE Standard 802.3-2018 requires certain MDIO accessi-

ble registers to exhibit latch low behavior. The idea is to allow

software that only intermittently reads these registers to detect

conditions that can be transitory or short lived. For example, the

AN_LINK_STATUS bit is required to latch low. When the device

exits from a reset or power-down state, the latching condition is not

active and the value of the AN_LINK_STATUS bit reflects the cur-

rent status of the link. However, if the link comes up and drops, the

latching condition is active. In this case, the AN_LINK_STATUS bit

reads as 0 even if the link has come back up again in the interim.

The latching condition is only cleared when the AN_LINK_STATUS

bit is read, ensuring the software had the opportunity to observe

that the link dropped.

One implication of this latch low behavior is that, if software wishes

to determine the current status of the link, it must perform two reads

of the AN_LINK_STATUS bit back to back. The first read is needed

to clear any active latching condition.

Another implication is that it is important that software take ac-

count of the interaction between MDIO accessible bits that share

a register address. For example, the AN_PAGE_RX bits and

AN_LINK_STATUS bits reside at the same register address. As

a result, reading the AN_PAGE_RX bits clears any active latching

condition associated with the AN_LINK_STATUS bits.

IEEE Duplicated Registers

The IEEE Standard 802.3-2018 covers a very wide range of stand-

ards and speeds, from 10 Mbps to 40 Gbps and higher, and

includes a large number of clauses. There are registers associated

with many clauses, and different PHYs can include different clauses

and combinations of clauses. Therefore, registers for common

functions like software reset, software power-down, loopback, and

so on, tend to be implemented in multiple clauses.

In the ADIN2111, the physical implementation of these registers is

in a single location, but they can be accessed at multiple address-

es. For example, the software reset bit, can be read or written in

all the following IEEE MMD locations and vendor specific register

locations:

►

PMA_SFT_RST

►

B10L_PMA_SFT_RST

►

PCS_SFT_RST

►

B10L_PCS_SFT_RST

►

CRSM_SFT_RST

In this example, these are the PMA/PMD, PCS, autonegotiation,

and Vendor Specific MMD 1 device address locations (per Table

43).

Having multiple address locations for the same register makes

the use of the device more complex than necessary, particularly

in relation to registers that have latch low or self clear access

permissions. This is an unavoidable consequence of the IEEE

standard.

The ADIN2111 data sheet only calls out a single recommended

address location for each of these IEEE registers to simplify the

operation and use of the device. In general, the registers intro-

duced in the 802.3cg (10BASE-T1L) section of the standard are

recommended over older (equivalent) registers. Often, registers in

a vendor specific address are recommended, particularly where a

all the IEEE register address locations covered by the 10BASE-T1L

standard when the start up completes after a power-on reset,

hardware reset, or software reset.

PHY Subsystem Registers Read Modify Write

Operation

All PHY subsystems register write operations must be performed

as read modify write operations. If this process is not followed, the

value of the register bits can inadvertently change.

SWITCH

Frame Forwarding on Receive

By default, the device drops all frames received. To receive frames,

set up the address filtering table, or change the default operation for

all receive frames.

Note that frames can be forwarded from one port to two destina-

tions: the other port and the host SPI port.

The device can be configured to forward up to 16 different MAC

addresses based on the MAC destination address (DA).

To receive frames with a particular DA, that DA has to be pro-

grammed to one of the 16 ADDR_FILT_x registers. Each register

is 32 bits wide. Therefore, for example, to program a DA of

08:00:00:5A:64:68 to ADDR_FILT_x0, write:

►

0x0800 to ADDR_FILT_UPR0

►

0x005A6468 to ADDR_FILT_LWR0

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