ADIN2111BCPZ-R7 datasheet(51/129 Pages) AD

51 / 129 page

Data Sheet

ADIN2111

SWITCH SPI

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Rev. A | 51 of 129

To forward frames with this DA to the host, set the TO_HOST bit

field within the ADDR_FILT_UPRn register to 1. To apply this rule,

set APPLY2PORT1 or APPLY2PORT2 to 1, accordingly.

MAC addresses can be masked using the ADDR_MSK_x registers.

For example, to receive all the MAC addresses in the range

0x8000005A64xx, write:

►

0xFFFF to ADDR_MSK_UPR0

►

0XFFFFFF00 to ADDR_MSK_LWR0

Frames that do not match any of the 16 ADDR_FILT_x regis-

ters are dropped by default. The user can select to forward

packages from unknown DAs to either the other port or the

host with the bit fields P2_FWD_UNK2P1, P1_FWD_UNK2P2,

P2_FWD_UNK2HOST, and P1_FWD_UNK2HOST in the MAC con-

figuration register (CONFIG2). Figure 31 shows the forwarding

algorithm. Frames received with a bad CRC or with RX_ERR

asserted from the PHYs, as well as runt and jabber frames, are

dropped and counted.

FORWARD

THE FRAME

TO THE

OTHER

PORT

YES

DA FOUND?

YES

APPLYTOPORTx = THIS PORT?

YES

TO HOST?

YES

TO_OTHER_PORT?

YES

TO_OTHER_PORT?

YES

PX_FWD_UNK2HOST

YES

PX_FWD_UNK2PX?

YES

PX_FWD_UNK2Px?

FORWARD

THE FRAME

TO THE

HOST

FORWARD

THE FRAME

TO THE

OTHER

PORT AND

THE HOST

DISCARD THE FRAME

AND INCREMENT

COUNTER

(RX_DROP_FILT_CNT)

X: PORT NUMBER (1 OR 2)

Figure 31. Frame Forwarding Algorithm

Receive Priority Queues

Each of the ADIN2111 PHYs has two different FIFOs on receive: a

high priority FIFO and a low priority FIFO.

By default, the low priority FIFO is configured to 12 kB, and

the high priority FIFO is configured to 8 kB. The sizes of these

FIFOs can be changed before receiving or transmitting any

frames via the P1_RX_LO_SIZE and P1_RX_HI_SIZE (Port 1)

and P2_RX_LO_SIZE and P2_RX_HI_SIZE (Port 2) fields in the

FIFO_SIZE register.

Statistics Counters

The ADIN2111 has fifteen 16-bit counters on each port that incre-

ment on frame transmit and receive. They roll over to 0 when the

maximum value of 65535 is reached and they are not cleared on

reading. Therefore, the counters must be read every four seconds

to ensure that the counters do not roll over the last value read by

the host.

Table 44. Port 1 and Port 2 Statistics Counters

Name1

Description

Px_RX_FRM_CNT

PORT Rx frame count

Px_RX_UCAST_CNT

PORT Rx unicast frame count

Px_RX_MCAST_CNT

PORT Rx multicast frame count

Px_RX_BCAST_CNT

PORT Rx broadcast frame count

Px_RX_CRC_ERR_CNT

PORT Rx CRC errored frame count

Px_RX_ALGN_ERR_CNT

PORT Rx alignment error count

Px_RX_PHY_ERR_CNT

PORT Rx PHY error count

Px_RX_LS_ERR_CNT

PORT Rx long and short frame error count

Px_TX_FRM_CNT

PORT Tx frame count

Px_TX_UCAST_CNT

PORT Tx unicast frame count

Px_TX_MCAST_CNT

PORT Tx multicast frame count

Px_TX_BCAST_CNT

PORT Tx broadcast frame count

Px_RX_DROP_FULL_CNT

PORT Rx frames dropped due to FIFO full

Px_RX_DROP_FILT_CNT

PORT Rx frames dropped due to filtering

Px_RX_IFG_ERR_CNT

PORT Rx frames received with interframe gap

(IFG) errors

1 One set of counters for each port. X represents the port number.

Receive Drop FIFO Full Counter

Before the first byte of a received frame is written into the appro-

priate receive FIFO on Port 1 (respectively Port 2), the space

in the FIFO is checked. If there is no space for at least 256

bytes, the frame is dropped and the P1_RX_DROP_FULL_CNT

(respectively P2_RX_DROP_FULL_CNT) counter increments. If

there is space for at least 256 bytes in the FIFO, the logic

writes the frame to the receive FIFO. If the received frame

exceeds 256 bytes and the receive FIFO fills, the frame

is dropped and the P1_RX_DROP_FULL_CNT (respectively

P2_RX_DROP_FULL_CNT) counter increments.

Note that if a frame is destined for both the host and the other

port, and the frame is not forwarded in one of the destination FIFOs

because it is full, the frame is not counted as a dropped frame.

Frame Receive and Transmit Errors

By default, received errored frames do not generate interrupts.

These frames are dropped and counted, and the software must

monitor the statistics counters. The static random-access memory

(SRAM) error correction code (ECC) error and transmit overflow

error are reported in the error status register (ERR_STATUS).

These errors result in the INT pin asserting an interrupt, unless

an error is masked using the error status mask register (ERR_STA-

TUS_MASK). See the SRAM ECC Error section and Transmit

Overflow Error section.

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