ADIN2111BCPZ-R7 datasheet(65/129 Pages) AD

65 / 129 page

Data Sheet

ADIN2111

REGISTERS

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Rev. A | 65 of 129

Table 60. Bit Descriptions for TTSCBL

Bits

Bit Name

Description

Reset

Access

[31:0]

TTSCL_B

Transmit Time Stamp B, Bits[31:0].

0x0

Transmit Time Stamp Capture Register C (High)

Address: 0x14, Reset: 0x00000000, Name: TTSCCH

This field contains the upper 32 bits of the captured time stamp for when the requested frame was transmitted.

Table 61. Bit Descriptions for TTSCCH

Bits

Bit Name

Description

Reset

Access

[31:0]

TTSCH_C

Transmit Time Stamp C Bits, [63:32].

0x0

Transmit Time Stamp Capture Register C (Low)

Address: 0x15, Reset: 0x00000000, Name: TTSCCL

This field contains the lower 32 bits of the captured time stamp for when the requested frame was transmitted.

Table 62. Bit Descriptions for TTSCCL

Bits

Bit Name

Description

Reset

Access

[31:0]

TTSCL_C

Transmit Time Stamp C, Bits[31:0].

0x0

MDIO Access Registers

Address: 0x20 to 0x27 (Increments of 1), Reset: 0x8C000000, Name: MDIOACCn

Use this register to access the PHY registers via the SPI to MDIO bridge.

Table 63. Bit Descriptions for MDIOACCn

Bits

Bit Name

Description

Reset

Access

MDIO_TRDONE

Transaction Done. This bit must be written to 0 by the SPI host to initiate an MDIO transaction. The

MACPHY sets this bit to 1 when the MDIO transaction completes.

0x1

R/W

MDIO_TAERR

Turnaround Error. The MACPHY sets this bit to 1 when a turnaround error occurs during the MDIO

transaction. If this occurs, the contents of the DATA field for read and read-post-increment-address

operations must be ignored.

0x0

[29:28]

MDIO_ST

Start of Frame. This field selects between Clause 45 and Clause 22 MDIO access.

0x0

R/W

00: Clause 45.

01: Clause 22.

[27:26]

MDIO_OP

Operation Code.

0x3

R/W

00: MD address command.

01: write command.

11: read command.

10: incremental read command.

[25:21]

MDIO_PRTAD

MDIO Port Address. This is the address of target port (PHY). This is called port address (PRTAD) for

Clause 45, and called PHY address (PHYAD) for Clause 22.

0x0

R/W

[20:16]

MDIO_DEVAD

MDIO Device Address. When using Clause 45, this is the device address. When using Clause 22, this is

the register address.

0x0

R/W

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