MCP47FXB2XT-EST datasheet(91/124 Pages) MICROCHIP

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DS20006368A-page 91

MCP47FXBX4/8

7.4.3

DISABLE CONFIGURATION BIT

(HIGH-VOLTAGE)

Figure 7-12 shows the formats for a single Modify Write

Protect or WiperLock Technology command.

A Modify Write Protect or WiperLock Technology com-

mand will only start an EEPROM write cycle (twc) after

a properly formatted command has been received and

the Stop condition occurs.

During an EEPROM write cycle, only serial commands

to volatile memory are accepted. All other serial com-

mands are ignored until the EEPROM write cycle (twc)

completes. This allows the host controller to operate on

the volatile DAC, the volatile VREF, Power-Down, Gain,

Status, and WiperLock Technology STATUS registers.

The EEWA bit in the STATUS register indicates the sta-

tus of an EEPROM write cycle.

FIGURE 7-12:

I2C Disable Command Sequence.

Note 1: This command sequence does not need to terminate (using the Stop bit) and can change to any other

desired command sequence (Enable, read or write).

2: This command byte is not required and the Stop bit may occur immediately after the 2nd ACK bit in this

sequence.

Memory Address

I2C ACK bit

I2C Start bit

I2C Slave Address

Disable command

Reserved, set to ‘0‘

I2C Stop bit(2)

Control byte

Disable command

Legend:

Disable command

I2C Write bit

Disable command

A I2C ACK bit(1)

.....

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