MCP47FXB2XT-EST datasheet(54/124 Pages) MICROCHIP

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MCP47FXBX4/8

DS20006368A-page 54

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4.1.1

POWER-ON RESET

The Power-on Reset is the case where the VDD has

power applied to it, ramping up from the VSS voltage

level. As the device powers up, the VOUT pin floats to

an unknown value. When VDD is above the transistor

threshold voltage of the device, the output starts to be

pulled low. After the VDD is above the POR/BOR trip

point (VBOR/VPOR), the resistor network’s wiper is

loaded with the POR value (midscale). The volatile

memory determines the analog output (VOUT) pin volt-

age. After the device is powered up, the user can

update the device’s memory.

When the rising VDD voltage crosses the VPOR trip

point, the following occurs:

• The nonvolatile DAC register value is latched into

volatile DAC register.

• The nonvolatile Configuration bit values are

latched into volatile Configuration bits.

• The POR Status bit is set (‘1’).

• The reset delay timer (tPORD) starts; when the

reset delay timer (tPORD) times out, the I2C serial

interface is operational. During this delay time, the

I2C interface will not accept commands.

• The Device Memory Address pointer is forced to

00h.

The Analog Output (VOUT) state is determined by the

state of the volatile Configuration bits and the DAC reg-

ister. This is called a Power-on Reset (event).

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

4.1.2

BROWN-OUT RESET

The Brown-out Reset occurs when a device has power

applied to it and that power (voltage) drops below the

specified range.

When the falling VDD voltage crosses the VPOR trip

point (BOR event), the following occurs:

• The serial interface is disabled.

• EEPROM writes are disabled.

• The device is forced into a Power-Down state

(PDnB:PDnA = ‘11’). Analog circuitry is turned off.

• The volatile DAC register is forced to 000h.

• Volatile Configuration bits VRnB:VRnA and Gx

are forced to ‘0’.

If the VDD voltage decreases below the VRAM voltage,

all volatile memory may become corrupted.

As the voltage recovers above the VPOR/VBOR voltage,

see Section 4.1.1 “Power-on Reset”.

Serial commands not completed due to a brown-out

condition may cause the memory location (volatile and

nonvolatile) to become corrupted.

Figure 4-1 illustrates the conditions for power-up and

power-down events under typical conditions.

FIGURE 4-1:

Power-On/Brown-Out Reset Operation.

Below Min.

Operating

Voltage

VPOR

VDD(MIN)

BOR,

Volatile DAC Register = 000h

Volatile VRnB:VRnA = ‘00’

VRAM

Volatile Gx = ‘0’

Volatile PDnB:PDnA = ‘11’

VBOR

POR Starts Reset Delay Timer;

After it Times Out, the Serial

Interface can Operate (if VDD  VDD(MIN))

Default

Device

Configuration

Latched into Volatile Configura-

tion Bits and DAC Register.

POR Status Bit is Set (‘1’)

Device in Unknown

State

Device

in POR

State

POR Forced

Active

Normal Operation

Device in

Power-

Down

State

Device in

Unknown

State

Volatile Memory Retains

Data Value

Volatile Memory

becomes Corrupted

TPORD

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