MCP47FXB2XT-EST datasheet(57/124 Pages) MICROCHIP

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DS20006368A-page 57

MCP47FXBX4/8

4.2.6

WIPERLOCK TECHNOLOGY

The MCP47FXBX4/8 WiperLock technology allows

application-specific device settings (DAC register and

configuration) to be secured without requiring the use

of an additional write-protect pin. There are two Con-

figuration bits (DLn:CLn) for each DAC channel (DAC0

through DAC7).

Dependent on the state of the DLn:CLn Configuration

bits, WiperLock technology prevents the serial

commands from the following actions on the DACn

registers and bits:

• Writing to the specified volatile DACn register

memory location

• Writing to the specified nonvolatile DACn register

memory location

• Writing to the specified volatile DACn Configura-

tion bits

• Writing to the specified nonvolatile DACn

Configuration bits

Each pair of these Configuration bits controls one of

the four modes. These modes are shown in Table 4-4.

The addresses for the Configuration bits are shown in

Table 4-4.

To modify the Configuration bits, the HVC pin must be

forced to the VIHH state and then an enable or disable

command must be received for the desired pair of

DAC register addresses.

Refer to Section 7.4.2 “Enable Configuration Bit

(High-Voltage)” and Section 7.4.3 “Disable Config-

uration Bit (High-Voltage)” commands for operation.

4.2.6.1

POR/BOR Operation with

WiperLock Technology Enabled

The WiperLock Technology state is not affected by a

POR/BOR event. A POR/BOR event will load the

volatile DACn register values with the nonvolatile or

default factory values (in case of volatile memory only

devices).

4.2.7

I2C SLAVE ADDRESS WRITE

PROTECT

The MCP47FEBX4/8 I2C Slave Address is stored in the

EEPROM memory. This allows the address to be mod-

ified to the application’s requirement. To ensure that the

I2C Slave address is not unintentionally modified, the

memory has a high-voltage write protect bit. This Con-

figurations bit is shown in Table 4-3.

Example: To modify the CL0 bit, the enable or disable

command specifies address 00h, while to modify the

DL0 bit, the enable or disable command specifies

address 10h.

Note:

During device communication, if the

device address/command combination is

invalid or an unimplemented address is

specified, the MCP47FXBX4/8 will NACK

that byte. To reset the I2C state machine,

the I2C communication must detect a Start

bit.

Note:

To modify the SALCK bit, the Enable or

Disable command specifies address 1Ah.

TABLE 4-3:

SALCK FUNCTIONAL

DESCRIPTION

SALCK Operation

The nonvolatile I2C Slave Address bits

(ADD6:ADD2) are locked

The nonvolatile I2C Slave Address bits

(ADD6:ADD2) are unlocked

TABLE 4-4:

WIPERLOCK™ TECHNOLOGY CONFIGURATION BITS - FUNCTIONAL DESCRIPTION

DLn:CLn(1)

Comments

DACn Wiper

DACn Configuration(1)

Volatile

Nonvolatile

Volatile

Nonvolatile

Locked

All DACn registers are locked.

Locked

Unlocked

Locked

All DACn registers are locked, except for volatile

DACn Configuration registers.

This allows operation of Power-Down modes.

Unlocked

Locked

Unlocked

Locked

Volatile DACn registers unlocked, nonvolatile

DACn registers locked.

Unlocked

All DACn registers are unlocked.

Note 1:

The state of these Configuration bits (DLn:CLn) is reflected in WLnB:WLnA bits, as shown in Register 4-6.

DAC Configuration bits include Voltage Reference Control bits (VRnB:VRnA), Power-Down Control bits

(PDnB:PDnA), and Output Gain bits (Gx).

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