MCP47FXB2XT-EST datasheet(90/124 Pages) MICROCHIP

90 / 124 page

MCP47FXBX4/8

DS20006368A-page 90

 2020 Microchip Technology Inc.

7.4

Modify Device Configuration Bit

Commands

These commands are used to program the device Con-

figuration bits. These commands require a high voltage

(VIHH) on the HVC pin.

The MCP47FXBX4/8 devices support the following

Modify Device Configuration Bit commands:

• Enable Configuration Bit (High-Voltage)

• Disable Configuration Bit (High-Voltage)

These Configuration bits are used to inhibit the DAC

values from inadvertent modification.

7.4.1

THE HIGH-VOLTAGE COMMAND

(HVC) SIGNAL

The High-Voltage command signal is used to indicate

that the command, or sequence of commands, are in

the High-Voltage mode. Signals >VIHH (~9.0V) on the

HVC pin put the device into High-Voltage mode. High-

Voltage commands allow the device’s WiperLock Tech-

nology and write-protect features to be enabled and

disabled.

7.4.2

ENABLE CONFIGURATION BIT

(HIGH-VOLTAGE)

Figure 7-11 shows the formats for a single Modify Write

Protect or WiperLock Technology command.

A Modify Write Protect or WiperLock Technology

command will only start an EEPROM write cycle (twc)

after a properly formatted command has been received

and the Stop condition occurs. During an EEPROM

write cycle, only serial commands to volatile memory

are accepted. All other serial commands are ignored

until the EEPROM write cycle (twc) completes. This

allows the host controller to operate on the volatile

DAC, the volatile VREF, Power-Down, Gain, Status, and

WiperLock technology STATUS registers. The EEWA

bit in the STATUS register indicates the status of an

EEPROM write cycle.

FIGURE 7-11:

I2C Enable Command Sequence.

Note 1: There is a required delay after the HVC

pin is driven to the VIHH level to the 1st

edge of the SCL pin.

2: Issuing an enable or disable command to

a nonvolatile location will cause an error

condition (A will be generated).

Note 1: This command sequence does not need to terminate (using the Stop bit) and can change to any other

desired command sequence (Enable, read or write).

2: This command byte is not required and the Stop bit may occur immediately after the 2nd ACK bit in this

sequence.

Memory Address

I2C ACK bit

I2C Start bit

I2C Slave Address

Enable command

Reserved, set to ‘0‘

I2C Stop bit(2)

Control byte

Enable command

Legend:

Enable command

I2C Write bit

Enable command

A I2C ACK bit(1)

.....

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