MCP47FXB2XT-EST datasheet(77/124 Pages) MICROCHIP

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DS20006368A-page 77

MCP47FXBX4/8

6.9

Entering High-Speed (HS) Mode

The I2C specification requires that a High-Speed mode

device be activated to operate in High-Speed

(3.4 Mbit/s) mode. This is accomplished by the master

sending a special address byte following the Start bit.

This byte is referred to as the High-Speed Master Mode

Code (HSMMC).

The device can now communicate at up to 3.4 Mbit/s

on SDA and SCL lines. The device will switch out of the

HS mode on the next Stop condition.

The master code is sent as follows:

Start condition (S)

High-Speed Master Mode Code (‘0000 1XXX’),

The XXX bits are unique to the HS master mode.

No Acknowledge (A)

After switching to the HS mode, the next transferred

byte is the I2C control byte, which specifies the device

to communicate with and any number of data bytes

plus acknowledgments. The master device can then

either issue a repeated Start bit to address a different

device (at high-speed) or a Stop bit to return to the

fast/standard bus speed. After the Stop bit, any other

master device (in a Multi-Master system) can arbitrate

for the I2C bus.

The MCP47FXBX4/8 devices do not acknowledge the

HS Select byte. However, upon receiving this

command, the device switches to HS mode.

Figure 6-3 illustrates the HS mode command

sequence.

For more information on the HS mode, or other I2C

modes, refer to the “NXP I2C Specification”.

6.9.1

SLOPE CONTROL

The slope control on the SDA output for the Fast/Stan-

dard Speed is different from the one of the High-Speed

clock modes of the interface.

6.9.2

PULSE GOBBLER

The pulse gobbler on the SCL pin is automatically

adjusted to suppress spikes < 10 ns during HS mode.

FIGURE 6-3:

HS Mode Sequence.

‘0000 1XXX’b

Slave Address

A/A

Data

S = Start bit

Sr = Repeated Start bit

A = Acknowledge bit

A = Not Acknowledge bit

R/W = Read/Write bit

R/W

P = Stop bit (Stop condition terminates HS Mode)

F/S mode

HS mode

HS mode continues

F/S mode

‘Slave Address’ R/W

HS Select Byte

Control Byte

Command/Data Byte(s)

Control Byte

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