MCP47FXB2XT-EST datasheet(71/124 Pages) MICROCHIP

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DS20006368A-page 71

MCP47FXBX4/8

5.5.1

EXITING POWER-DOWN

When the device exits Power-Down mode, the

following occurs:

• Disabled circuits (op amp, resistor ladder, et al.)

are turned on

• The resistor ladder is connected to the selected

Reference Voltage (VRL)

• The selected pull-down resistor is disconnected

•The VOUT output will be driven to the voltage

represented by the volatile DAC register’s value

and Configuration bits

The VOUT output signal requires time as these circuits

are powered up and the output voltage is driven to the

specified value as determined by the volatile DAC

The following events change the PDnB:PDnA bits to ‘00’

and therefore exit the Power-Down mode. These are:

•Any I2C WRITE command where the PDnB:PDnA

bits are ‘00’

•I2C General Call Wake-up command

•I2C General Call Reset command (if nonvolatile

PDnB:PDnA bits are ‘00’).

5.5.2

RESET COMMANDS

When the MCP47FXBX4/8 devices are in the valid

operating voltage range, the I2C General Call Reset

command forces a Reset event. This is similar to the

POR, except that the Reset delay timer is not started.

If the I2C interface bus does not seem to be respon-

sive, the technique shown in Section 8.1.3 “Software

I2C Interface Reset Sequence” can be used to force

the I2C interface to reset.

5.6

DAC Registers, Configuration

Bits, and Status Bits

The MCP47FXBX4/8 device family has both volatile

and nonvolatile (EEPROM) memory options. Table 4-2

shows the volatile and nonvolatile memory and their

interaction due to a POR event.

There are five Configuration bits, DAC registers, and

two volatile status bits in both the volatile and nonvola-

tile memory. The DAC registers (volatile and nonvola-

tile) will be either twelve bits (MCP47FXB2X), ten bits

(MCP47FEB1X), or eight bits (MCP47FXB0X) wide.

When the device is first powered-up, it automatically

uploads the EEPROM memory values or factory

default values (in case of MCP47FVBXX devices) to

the volatile memory. The volatile memory determines

the analog output (VOUT) pin voltage. After the device

is powered-up, the user can update the memory.

This memory is read and written through the I2C inter-

face. See Section 6.0 “I2C Serial Interface Module”

and Section 7.0 “I2C Device Commands” for more

details on reading and writing the device’s memory.

When the nonvolatile memory is written, the device

starts writing the EEPROM cell at the Acknowledge

pulse of the WRITE single memory location command.

bits and Table 4-2 shows the factory default value of a

POR/BOR event for the device Configuration bits.

There are two status bits. These are only in volatile

memory and indicate the status of the device. The POR

bit indicates if the device VDD is above or below the

POR trip point. During normal operation, this bit should

be ‘1’. The EEWA bit indicates if an EEPROM write

cycle is in progress. While the EEWA bit is ‘1’ (during

the EEPROM writing), all commands are ignored,

except for the READ command.

Note:

Since the op amp and resistor ladder are

powered-off (0V), the op amp’s Input

Voltage (VW) can be considered 0V. There

delay

(TPDD) between the

PDnB:PDnA bits updating to ‘00’ and the

op amp driving the VOUT output. The op

amp’s settling time (from 0V) needs to be

taken into account to ensure the VOUT

voltage reflects the selected value.

Note:

On quad-channel devices, after issuing a

General Call Wake-up command, a

current higher than normal will be drawn.

To avoid this issue, on quad-channel

devices, General Call Wake-up should be

followed by a General Call Reset

command. No other functionality is

affected.

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