SIO1007 datasheet(77/108 Pages) MICROCHIP

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DS00002020A-page 77

SIO1007

18.4.43

CR2C

CR2C can only be accessed in the configuration state and after the CSR has been initialized to 2CH. Bits D[3:0] of this

return 0 when read. Any unselected DMA Request output (DRQ) is in tristate.

18.4.44

CR2D

CR2D can only be accessed in the configuration state and after the CSR has been initialized to 2DH. CR2D is used to

set the IR Half Duplex Turnaround Delay Time for the IR port. This value is 0 to 25.5msec in 100µsec increments.

The IRCC v2.0 block includes an 8-bit IR Half Duplex Time-out register in SCE Register Block 5, Address 1 that interacts

with configuration register CR2D. These two registers behave like the other IRCC Legacy controls where either source

uniformly updates the value of both registers when either register is explicitly written using IOW or following a device-

level POR. IRCC software resets do not affect these registers.

The IR Half Duplex Time-out is programmable from 0 to 25.5mS in 100

S increments, as follows:

IR HALF DUPLEX TIME-OUT = (CR2D) x 100

S

18.4.45

CR2E

CR2E can only be accessed in the configuration state and after the CSR has been initialized to 2EH. CR2E is directly

connected to SCE Register Block Three, Address 0x05 in the IRCC v2.0 block.

TABLE 18-37: CR2C

SCE (FIR) DMA Select Register

Type: R/W

Default: 0X0F ON VCC POR

BIT NO.

BIT NAME

DESCRIPTION

3:0

DMA Select

BIT3

BIT2

BIT1

BIT0

DMA SELECTED

RESERVED

DMA1

DMA2

DMA3

RESERVED

NONE

7:4

Reserved

Read Only. A read returns 0.

TABLE 18-38: CR2D

IR Half Duplex Timeout

Type: R/W

Default: 0X03 ON VCC POR

BIT NO.

BIT NAME

DESCRIPTION

0-7

IR Half Duplex Time

Out

These bits are used to set the IR Half Duplex Turnaround Delay Time for

the IR port. This value is 0 to 25.5msec in 100µsec increments.

TABLE 18-39: CR2E

Software Select A

Type: R/W

Default: 0X00 ON VCC POR

BIT NO.

BIT NAME

DESCRIPTION

0-7

Software Select A

These bits are directly connected to SCE Register Block Three, Address

0x05 in the IRCC v2.0 block.

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