SIO1007 datasheet(31/108 Pages) MICROCHIP

31 / 108 page

TABLE 9-5:

Regiser Address

(Note 9-4)

Reg. Symbol

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

ADDR = 0

DLAB = 0

Receive Buffer

Only)

RBR

Data Bit 0

(Note 9-5)

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

ADDR = 0

DLAB = 0

Transmitter Holding

Only)

THR

Data Bit 0

Data Bit 1

Data Bit 2

Data Bit 3

Data Bit 4

Data Bit 5

Data Bit 6

Data Bit 7

ADDR = 1

DLAB = 0

Interrupt Enable

IER

Enable Received

Data Available

Interrupt

(ERDAI)

Enable Trans-

mitter Holding

Interrupt

(ETHREI)

Enable

Receiver Line

Status

Interrupt

(ELSI)

Enable

Modem Status

Interrupt

(EMSI)

ADDR = 2

Interrupt Ident.

Only)

IIR

"0" if Interrupt

Pending

Interrupt ID Bit

Interrupt ID

Bit

Interrupt ID Bit

(Note 9-9)

FIFOs

Enabled

(Note 9-9)

FIFOs Enabled

(Note 9-9)

ADDR = 2

FIFO Control

Only)

FCR

(Note 9-11)

FIFO Enable

RCVR FIFO

Reset

XMIT FIFO

Reset

DMA Mode

Select

(Note 9-11)

Reserved

RCVR Trigger

LSB

RCVR Trigger

MSB

ADDR = 3

Line Control

LCR

Word Length

Select Bit 0

(WLS0)

Word Length

Select Bit 1

(WLS1)

Number of

Stop Bits

(STB)

Parity Enable

(PEN)

Even Parity

Select

(EPS)

Stick Parity

Set Break

Divisor Latch

Access Bit

(DLAB)

ADDR = 4

MODEM Control

MCR

Data Terminal

Ready (DTR)

Request to

Send (RTS)

OUT1

(Note 9-7)

OUT2

(Note 9-7)

Loop

ADDR = 5

Line Status

LSR

Data Ready

(DR)

Overrun Error

(OE)

Parity Error

(PE)

Framing Error

(FE)

Break

Interrupt (BI)

Transmitter

Holding Register

(THRE)

Transmitter

Empty

(TEMT)

(Note 9-6)

Error in RCVR

FIFO (Note 9-9)

ADDR = 6

MODEM Status

MSR

Delta Clear to

Send (DCTS)

Delta Data Set

Ready (DDSR)

Trailing Edge

Ring Indicator

(TERI)

Delta Data

Carrier Detect

(DDCD)

Clear to

Send (CTS)

Data Set Ready

(DSR)

Ring Indicator

(RI)

Data Carrier

Detect (DCD)

ADDR = 7

Scratch Register

(Note 9-8)

SCR

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

ADDR = 0

DLAB = 1

Divisor Latch (LS)

DDL

Bit 0

Bit 1

Bit 2

Bit 3

Bit 4

Bit 5

Bit 6

Bit 7

ADDR = 1

DLAB = 1

Divisor Latch (MS)

DLM

Bit 8

Bit 9

Bit 10

Bit 11

Bit 12

Bit 13

Bit 14

Bit 15

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