SIO1007 datasheet(49/108 Pages) MICROCHIP

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DS00002020A-page 49

SIO1007

14.4

GPIO Operation

The operation of the GPIO ports is illustrated in Figure 14-1.

When a GPIO port is programmed as an input, reading it through the GPIO data register latches either the inverted or

non-inverted logic value present at the GPIO pin. Writing to a GPIO port that is programmed as an input has no effect

(Table 14-4).

When a GPIO port is programmed as an output, the logic value or the inverted logic value that has been written into the

GPIO data register is output to the GPIO pin. Reading from a GPIO port that is programmed as an output returns the

last value written to the data register (Table 14-4).

The SIO1007 provides 16 GPIOs that can directly generate a PME. See the table in the next section. The GPIO Polarity

Registers in the Configuration section select the edge on these GPIO pins that will set the associated status bit in the

PME_STS1 – PME_STS3 registers. The default is the low-to-high edge. If the corresponding enable bit in the PME_EN1

– PME_EN3 registers and the PME_EN bit in the PME_EN register is set, a PME will be generated. These registers are

located in the Runtime Registers Block, which is located at the address contained in the configuration registers CR30.

The PME status bits for the GPIOs are cleared on a write of ‘1’. In addition, the SIO1007 provides 10 GPIOs that can

directly generate an SMI. See the table in the next section.

FIGURE 14-1:

GPIO FUNCTION ILLUSTRATION

Note:

Figure 14-1 is for illustration purposes only and in not intended to suggest specific implementation details.

TABLE 14-4:

GPIO READ/WRITE BEHAVIOR

Host Operation

GPIO Input Port

GPIO Output Port

READ

LATCHED VALUE OF GPIO PIN

LAST WRITE TO GPIO DATA

WRITE

NO EFFECT

BIT PLACED IN GPIO DATA

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