| Os motores de busca de Datasheet de Componentes eletrônicos |
|
SIO1007 Folha de dados(PDF) 50 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
SIO1007 Folha de dados(HTML) 50 Page - Microchip Technology |
|
50 / 108 page ![]() SIO1007 DS00002020A-page 50 2005 - 2015 Microchip Technology Inc. 14.5 GPIO PME and SMI Functionality The provides SIO1007 provides 16 GPIOs that can directly generate a PME. See the table in the next section. The GPIO Polarity Registers in the Configuration section select the edge on these GPIO pins that will set the associated status bit in the PME_STS1 – PME_STS3 registers. The default is the low-to-high edge. If the corresponding enable bit in the PME_EN1 – PME_EN3 registers and the PME_EN bit in the PME_EN register is set, a PME will be generated. These registers are located in the Runtime Registers Block, which is located at the address contained in the configuration reg- isters CR30. The PME status bits for the GPIOs are cleared on a write of ‘1’. In addition, the SIO1007 provides 8 GPIOs that can directly generate an SMI. The following GPIOs are dedicated wakeup GPIOs with a status and enable bit in the PME status and enable registers: GP10-GP17 GP30-GP37 This following is the list of PME status and enable registers for their corresponding GPIOs: PME_STS1 and PME_EN1 for GP10-GP17 PME_STS3 and PME_EN3 for GP30-GP37 The following GPIOs can directly generate an SMI and have a status and enable bit in the SMI status and enable reg- isters. GP10-GP17 The following SMI status and enable registers for these GPIOs: SMI_STS1 and SMI_EN1 for GP10-17 The following table summarizes the PME and SMI functionality for each GPIO. Note 14-3 Since GP12 can be used to generate an SMI and as the IO_SMI# output, do not enable GP12 to generate an SMI (by setting bit 2 of the SMI Enable Register 1) if the IO_SMI# function is selected on the GP12 pin. Use GP12 to generate an SMI event only if the SMI output is enabled on the Serial IRQ stream. TABLE 14-5: PME AND SMI FUNCTIONALITY GPIO PME Status and Enable Registers SMI Status and Enable Registers Output Buffer Power GP10-GP11 PME_STS1 & PME_EN1 SMI_STS1 and SMI_EN1 VCC GP12 (See Note 14-3) VCC GP13-GP17 VCC GP30-GP37 PME_STS1 & PME_EN1 None VCC |
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |