 |
Os motores de busca de Datasheet de Componentes eletrônicos |
|
|
Os motores de busca de Datasheet de Componentes eletrônicos |
|
SIO1007 Folha de dados(PDF) 53 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
SIO1007 Folha de dados(HTML) 53 Page - Microchip Technology |
|
|
53 / 108 page  2005 - 2015 Microchip Technology Inc. DS00002020A-page 53 SIO1007 17.0 RUNTIME REGISTERS 17.1 Runtime Registers Block Summary The runtime registers are located at the address programmed in the Runtime Register Block Base Address configura- tion registers (high and low byte) located in CR30 & CR21. The part performs 16-bit address qualification on the Runtime Register Base Address (bits[15:0] are decoded). The runtime register block may be located within the range 0x0100- 0xFFFF on 16-byte boundaries. Decodes are disabled if the Runtime Register Base Address is located below 0x100. These registers are powered by VTR. Note 17-1 Reserved bits return 0 on read. 17.2 Runtime Registers Block Description TABLE 17-1: RUNTIME REGISTER BLOCK SUMMARY Register Offset (HEX) Type PCI Reset VCC POR VTR POR Register 00 R/W - - 0x00 PME_STS 01 R/W - - 0x00 PME_EN 02 R/W - Note 17-1 0x00 PME_STS1 03 R/W - - 0x00 PME_STS2 04 R/W - Note 17-1 0x00 PME_STS3 05 R/W - - 0x00 PME_EN1 06 R/W - - 0x00 PME_EN2 07 R/W - - 0x00 PME_EN3 08 R/W - Note 17-1 0x00 SMI_STS1 09 R/W - - 0x00 SMI_STS2 0A R/W - - 0x00 SMI_EN1 0B R/W - - 0x00 SMI_EN2 0C R/W - Note 17-1 0x00 GP1 0D R - - 0x00 Reserved 0E R/W - Note 17-1 0x00 GP3 0F R - - 0x00 Reserved TABLE 17-2: RUNTIME REGISTERS BLOCK DESCRIPTION Name/Default Register Offset Description PME_STS Default = 0x00 on VTR POR 00 (R/W) Bit[0] PME_Status = 0 (default) = 1 Set when SIO1007 would normally assert the IO_PME# signal, independent of the state of the PME_En bit. Bit[7:1] Reserved Note: PME_Status is not affected by Vcc POR, SOFT RESET or PCI RESET. Writing a “1” to PME_Status will clear it and cause the SIO1007 to stop asserting IO_PME#, in enabled. Writing a “0” to PME_Status has no effect. PME_EN Default = 0x00 on VTR POR 01 (R/W) Bit[0] PME_En = 0 IO_PME# signal assertion is disabled (default) = 1 Enables SIO1007 to assert IO_PME# signal Bit[7:1] Reserved PME_EN is not affected by Vcc POR, SOFT RESET or PCI RESET |
|
Ligação URL |
| ALLDATASHEET é útil para você? [ DONATE ] |
Sobre Alldatasheet | Publicidade | Contato conosco | Privacy Policy | Link para a ficha técnica | roca de Link | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Portuguese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
