HD64F2149YV datasheet(930/1075 Pages) RENESAS

930 / 1075 page

Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 902 of 1044

REJ09B0280-0300

LADR3H—LPC Channel 3 Address Register H

H'FE34

HIF (LPC)

LADR3L—LPC Channel 3 Address Register L

H'FE35

HIF (LPC)

LADR3H

LADR3L

Bit

76543

210765

43210

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

—

Bit 1 TWRE

Initial value

00000

000000

00000

Read/Write

R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

↓↓↓↓↓

↓↓↓↓↓↓

↓↓

↓

IDR3, ODR3,

STR3 address

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

1/0

Bit 1

↓↓↓↓↓

↓↓↓↓↓↓

↓

TWR0–TWR15

address

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9

Bit 8

Bit 7

Bit 6

Bit 5

Bit 4 1/0

1/0

Channel 3 address bits 15 to 3 and 1

the following table.

I/O address

Transfer

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

cycle

Host register selection

Bit 4

Bit 3

Bit 1

I/O write

IDR3 write, C/

D3 ← 0

Bit 4

Bit 3

Bit 1

I/O write

IDR3 write, C/

D3 ← 1

Bit 4

Bit 3

Bit 1

I/O read

ODR3 read

Bit 4

Bit 3

Bit 1

I/O read

STR3 read

Bit 4

0000

I/O write

TWR0MW write

Bit 4

0001

I/O write

TWR1 write to TWR15 write

••

•

1111

Bit 4

0000

I/O read

TWR0SW read

Bit 4

0001

I/O read

TWR1 read to TWR15 read

••

•

1111

Two-way register enable

LADR3L

Bit 0

Description

TWRE

TWR operation is disabled

TWR-related I/O address match determination is halted

TWR operation is enabled

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