HD64F2149YV datasheet(932/1075 Pages) RENESAS

932 / 1075 page

Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 904 of 1044

REJ09B0280-0300

SIRQCR1—SERIRQ Control Register 1

H'FE37

HIF (LPC)

IRQ11E3

R/W

—

IRQ10E3

R/W

—

IRQ9E3

R/W

—

IRQ6E3

R/W

—

IRQ11E2

R/W

—

IRQ6E2

R/W

—

IRQ10E2

R/W

—

IRQ9E2

R/W

—

Bit

Initial value

Slave Read/Write

Host Read/Write

HIRQ6 interrupt enable 2

HIRQ6 interrupt request by OBF2 and IRQ6E2 is disabled

[Clearing conditions]

• Writing 0 to IRQ6E2

• LPC hardware reset, LPC software reset

• Clearing OBF2 to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ6 interrupt request by setting OBF2 to 1 is enabled

[When IEDIR = 1]

HIRQ6 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ6E2 = 0

HIRQ9 interrupt enable 2

HIRQ9 interrupt request by OBF2 and IRQ9E2 is disabled

[Clearing conditions]

• Writing 0 to IRQ9E2

• LPC hardware reset, LPC software reset

• Clearing OBF2 to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ9 interrupt request by setting OBF2 to 1 is enabled

[When IEDIR = 1]

HIRQ9 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ9E2 = 0

HIRQ10 interrupt enable 2

HIRQ10 interrupt request by OBF2 and IRQ10E2 is disabled

[Clearing conditions]

• Writing 0 to IRQ10E2

• LPC hardware reset, LPC software reset

• Clearing OBF2 to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ10 interrupt request by setting OBF2 to 1 is enabled

[When IEDIR = 1]

HIRQ10 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ10E2 = 0

HIRQ11 interrupt enable 2

HIRQ11 interrupt request by OBF2 and IRQ11E2 is disabled

[Clearing conditions]

• Writing 0 to IRQ11E2

• LPC hardware reset, LPC software reset

• Clearing OBF2 to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ11 interrupt request by setting OBF2 to 1 is enabled

[When IEDIR = 1]

HIRQ11 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ11E2 = 0

HIRQ6 interrupt enable 3

HIRQ6 interrupt request by OBF3A and IRQ6E3 is disabled

[Clearing conditions]

• Writing 0 to IRQ6E3

• LPC hardware reset, LPC software reset

• Clearing OBF3A to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ6 interrupt request by setting OBF3A to 1 is enabled

[When IEDIR = 1]

HIRQ6 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ6E3 = 0

HIRQ9 interrupt enable 3

HIRQ9 interrupt request by OBF3A and IRQ9E3 is disabled

[Clearing conditions]

• Writing 0 to IRQ9E3

• LPC hardware reset, LPC software reset

• Clearing OBF3A to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ9 interrupt request by setting OBF3A to 1 is enabled

[When IEDIR = 1]

HIRQ9 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ9E3 = 0

HIRQ10 interrupt enable 3

HIRQ10 interrupt request by OBF3A and IRQ10E3 is disabled

[Clearing conditions]

• Writing 0 to IRQ10E3

• LPC hardware reset, LPC software reset

• Clearing OBF3A to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ10 interrupt request by setting OBF3A to 1 is enabled

[When IEDIR = 1]

HIRQ10 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ10E3 = 0

HIRQ11 interrupt enable 3

HIRQ11 interrupt request by OBF3A and IRQ11E3 is disabled

[Clearing conditions]

• Writing 0 to IRQ11E3

• LPC hardware reset, LPC software reset

• Clearing OBF3A to 0 (when IEDIR = 0)

[When IEDIR = 0]

HIRQ11 interrupt request by setting OBF3A to 1 is enabled

[When IEDIR = 1]

HIRQ11 interrupt is requested

[Setting condition]

• Writing 1 after reading IRQ11E3 = 0

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