HD64F2149YV datasheet(934/1075 Pages) RENESAS

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Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 906 of 1044

REJ09B0280-0300

HICR1—Host Interface Control Register 1

H'FE41

HIF (LPC)

LPCBSY

—

CLKREQ

—

IRQBSY

—

LRSTB

R/W

—

SDWNB

R/W

—

LSCIB

R/W

—

PMEB

R/W

—

LSMIB

R/W

—

Bit

Initial value

Slave Read/Write

Host Read/Write

LSCI output bit

HICR0

Bit 0

HICR1

Bit 0

LSCIB

LSCIE

Description

LSCI output disabled, other function of pin enabled

LSCI output enabled, LSCI pin output goes to 0 level

LSCI output enabled, LSCI pin output is high-impedance

LSMI output bit

HICR0

Bit 1

HICR1

Bit 1

LSMIB

LSMIE

Description

LSMI output disabled, other function of pin enabled

LSMI output enabled,

LSMI pin output goes to 0 level

LSMI output enabled,

LSMI pin output is high-impedance

PME output bit

HICR0

Bit 2

HICR1

Bit 2

PMEB

PMEE

Description

PME output disabled, other function of pin enabled

PME output enabled,

PME pin output goes to 0 level

PME output enabled,

PME pin output is high-impedance

LPC software shutdown bit

Normal state

[Clearing conditions]

• Writing 0

• LPC hardware reset or LPC software reset

• LPC hardware shutdown

(falling edge of

LPCPD signal when SDWNE = 1)

• LPC hardware shutdown release

(rising edge of

LPCPD signal when SDWNE = 0)

LPC software shutdown state

[Setting condition]

• Writing 1 after reading SDWNB = 0

LPC software reset bit

Normal state

[Clearing conditions]

• Writing 0

• LPC hardware reset

LPC software reset state

[Setting condition]

• Writing 1 after reading LRSTB = 0

SERIRQ busy

SERIRQ transfer frame wait state

[Clearing conditions]

• LPC hardware reset or LPC software reset

• LPC hardware shutdown or LPC software shutdown

• End of SERIRQ transfer frame

SERIRQ transfer processing in progress

[Setting condition]

• Start of SERIRQ transfer frame

LCLK request

No LCLK restart request

[Clearing conditions]

• LPC hardware reset or LPC software reset

• LPC hardware shutdown or LPC software shutdown

• SERIRQ is set to continuous mode

• There are no further interrupts for transfer to the host in quiet mode

LCLK restart request issued

[Setting condition]

• In quiet mode, SERIRQ interrupt output becomes necessary while LCLK is stopped

LPC busy

Host interface is in transfer cycle wait state

• Bus idle, or transfer cycle not subject to processing is in progress

• Cycle type or address indeterminate during transfer cycle

[Clearing conditions]

• LPC hardware reset or LPC software reset

• LPC hardware shutdown or LPC software shutdown

• Forced termination (abort) of transfer cycle subject to processing

• Normal termination of transfer cycle subject to processing

Host interface is performing transfer cycle processing

[Setting condition]

• Match of cycle type and address

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