HD64F2149YV datasheet(931/1075 Pages) RENESAS

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Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 903 of 1044

REJ09B0280-0300

SIRQCR0—SERIRQ Control Register 0

H'FE36

HIF (LPC)

—

R/W

—

IEDIR

R/W

—

SMIE3B

R/W

—

SMIE3A

R/W

—

IRQ1E1

R/W

—

SMIE2

R/W

—

IRQ12E1

R/W

—

Bit

Initial value

Slave Read/Write

Host Read/Write

HIRQ1 interrupt enable 1

HIRQ1 interrupt request by OBF1 and IRQ1E1 is disabled

[Clearing conditions]

• Writing 0 to IRQ1E1

• LPC hardware reset, LPC software reset

• Clearing OBF1 to 0

HIRQ1 interrupt request by setting OBF1 to 1 is enabled

[Setting condition]

• Writing 1 after reading IRQ1E1 = 0

HIRQ12 interrupt enable 1

HIRQ12 interrupt request by OBF1 and IRQ12E1 is disabled

[Clearing conditions]

• Writing 0 to IRQ12E1

• LPC hardware reset, LPC software reset

• Clearing OBF1 to 0

HIRQ12 interrupt request by setting OBF1 to 1 is enabled

[Setting condition]

• Writing 1 after reading IRQ12E1 = 0

SMI interrupt enable 2

SMI interrupt request by OBF2 and SMIE2 is disabled

[Clearing conditions]

• Writing 0 to SMIE2

• LPC hardware reset, LPC software reset

• Clearing OBF2 to 0 (when IEDIR = 0)

[When IEDIR = 0] SMI interrupt request by setting OBF2 to 1 is enabled

[When IEDIR = 1] SMI interrupt is requested

[Setting condition]

• Writing 1 after reading SMIE2 = 0

SMI interrupt enable 3A

SMI interrupt request by OBF3A and SMIE3A is disabled

[Clearing conditions]

• Writing 0 to SMIE3A

• LPC hardware reset, LPC software reset

• Clearing OBF3A to 0 (when IEDIR = 0)

[When IEDIR = 0] SMI interrupt request by setting OBF3A to 1 is enabled

[When IEDIR = 1] SMI interrupt is requested

[Setting condition]

• Writing 1 after reading SMIE3A = 0

SMI interrupt enable 3B

SMI interrupt request by OBF3B and SMIE3B is disabled

[Clearing conditions]

• Writing 0 to SMIE3B

• LPC hardware reset, LPC software reset

• Clearing OBF3B to 0 (when IEDIR = 0)

[When IEDIR = 0] SMI interrupt request by setting OBF3B to 1 is enabled

[When IEDIR = 1] SMI interrupt is requested

[Setting condition]

• Writing 1 after reading SMIE3B = 0

Interrupt enable direct mode

Host interrupt is requested when host interrupt enable bit and corresponding OBF are both set to 1

Host interrupt is requested when host interrupt enable bit is set to 1

Quiet/continuous mode flag

Continuous mode

[Clearing conditions]

• LPC hardware reset, LPC software reset

• Specification by SERIRQ transfer cycle stop frame

Quiet mode

[Setting condition]

• Specification by SERIRQ transfer cycle stop frame

Reserved

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