HD64F2149YV datasheet(929/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 901 of 1044

REJ09B0280-0300

STR1—Status Register 1

H'FE3A

HIF (LPC)

STR2—Status Register 2

H'FE3E

HIF (LPC)

DBU17

R/W

DBU16

R/W

DBU15

R/W

DBU14

R/W

OBF1

R/(W)*

DBU12

R/W

IBF1

Bit

Initial value

Slave Read/Write

Host Read/Write

• STR1

DBU27

R/W

DBU26

R/W

DBU25

R/W

DBU24

R/W

OBF2

R/(W)*

DBU22

R/W

IBF2

Bit

Initial value

Slave Read/Write

Host Read/Write

• STR2

Output data register full

[Clearing condition]

Host reads ODR using I/O read cycle,

or slave writes 0 to OBF bit

[Setting condition]

Slave writes to ODR

Input data register full

[Clearing condition]

Slave reads IDR

[Setting condition]

Host writes to IDR using I/O write cycle

Command/data

Input data register (IDR) contents are data

Input data register (IDR) contents are a command

Note: * Only 0 can be written, to clear the flag.

User-defined bits

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