HD64F2149YV datasheet(645/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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Fabricante Electrônico	RENESAS [Renesas Technology Corp]

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Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 617 of 1044

REJ09B0280-0300

HICR2 Bit 6—LPC Reset Interrupt Flag (LRST): Interrupt flag that generates an ERRI

interrupt when an LPC hardware reset occurs.

HICR2

Bit 6

LRST

Description

[Clearing condition]

(Initial value)

• Writing 0 after reading LRST = 1

[Setting condition]

• LRESET pin falling edge detection

HICR2 Bit 5—LPC Shutdown Interrupt Flag (SDWN): Interrupt flag that generates an ERRI

interrupt when an LPC hardware shutdown request is generated.

HICR2

Bit 5

SDWN

Description

[Clearing conditions]

(Initial value)

• Writing 0 after reading SDWN = 1

• LPC hardware reset (LRESET pin falling edge detection)

• LPC software reset (LRSTB = 1)

[Setting condition]

• LPCPD pin falling edge detection

HICR2 Bit 4—LPC Abort Interrupt Flag (ABRT): Interrupt flag that generates an ERRI

interrupt when a forced termination (abort) of an LPC transfer cycle occurs.

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