HD64F2149YV datasheet(620/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 18A Host Interface X-Bus Interface (XBS)

Rev. 3.00 Jan 18, 2006 page 592 of 1044

REJ09B0280-0300

Bit 0—Output Buffer Full (OBF): Set to 1 when the slave processor writes to ODR1. Cleared to

0 when the host processor reads ODR.

Bit 0

OBF

Description

[Clearing condition]

When the host processor reads ODR or the slave writes 0 in the OBF bit (Initial value)

[Setting condition]

When the slave processor writes to ODR

Table 18A.3 shows the conditions for setting and clearing the STR flags.

Table 18A.3 Set/Clear Timing for STR Flags

Flag

Setting Condition

Clearing Condition

Rising edge of host’s write signal

(

IOW) when HA0 is high

Rising edge of host’s write signal (

IOW) when

HA0 is low

IBF*

Rising edge of host’s write signal

(

IOW) when writing to IDR1

Falling edge of slave’s internal read signal (

RD)

when reading IDR1

OBF

Falling edge of slave’s internal write

signal (

WR) when writing to ODR1

Rising edge of host’s read signal (

IOR) when

reading ODR1

Note:

The IBF flag setting and clearing conditions are different when the fast A20 gate is

used. For details see table 18A.7.

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