HD64F2149YV datasheet(622/1075 Pages) RENESAS

622 / 1075 page

Section 18A Host Interface X-Bus Interface (XBS)

Rev. 3.00 Jan 18, 2006 page 594 of 1044

REJ09B0280-0300

Table 18A.4 Host Interface Channel Selection and Pin Operation

HI12E

CS2E

CS3E

CS4E

Operation

——

—

Host interface functions halted

Host interface channel 1 only operating

Operation of channels 2 to 4 halted

(No operation as

CS2 or ECS2, CS3, and CS4 inputs. Pins

P43, P81, P90, and PB0 to PB3 operate as I/O ports.)

Host interface channel 1 and 4 functions operating

Operation of channels 2 and 3 halted

(No operation as

CS2 or ECS2 and CS3 inputs. Pins P43, P81,

P90, PB0, and PB2 operate as I/O ports.)

Host interface channel 1 and 3 functions operating

Operation of channels 2 and 4 halted

(No operation as

CS2 or ECS2 and CS4 inputs. Pins P43, P81,

P90, PB1, and PB3 operate as I/O ports.)

Host interface channel 1, 3, and 4 functions operating

Operation of channel 2 halted

(No operation as

CS2 or ECS2 input. Pins P43, P81, and P90

operate as I/O ports.)

Host interface channel 1 and 2 functions operating

Operation of channels 3 and 4 halted

(No operation as

CS3 and CS4 inputs. Pins PB0 to PB3

operate as I/O ports.)

Host interface channel 1, 2, and 4 functions operating

Operation of channel 3 halted

(No operation as

CS3 input. Pins PB0 and PB2 operate as I/O

ports.)

Host interface channel 1 to 3 functions operating

Operation of channel 4 halted

(No operation as

CS4 input. Pins PB1 and PB3 operate as I/O

ports.)

Host interface channel 1 to 4 functions operating

For host read/write timing, see section 25.3.4, Timing of On-Chip Supporting Modules.

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