HD64F2149YV datasheet(618/1075 Pages) RENESAS

618 / 1075 page

Section 18A Host Interface X-Bus Interface (XBS)

Rev. 3.00 Jan 18, 2006 page 590 of 1044

REJ09B0280-0300

HICR2 Bit 0—Reserved: Do not set to 1.

18A.2.4 Input Data Register (IDR)

Bit

Initial value

Slave Read/Write

Host Read/Write

IDR7

—

IDR6

—

IDR5

—

IDR4

—

IDR3

—

IDR0

—

IDR2

—

IDR1

—

IDRn (n = 1 to 4) is an 8-bit read-only register to the slave processor, and an 8-bit write-only

CSn (n = 1 to 4) is low, information on the host data bus is

written into IDRn at the rising edge of

IOW. The HA0 state is also latched into the C/D bit in

STRn to indicate whether the written information is a command or data.

The initial values of IDR after a reset and in standby mode are undetermined.

18A.2.5 Output Data Register (ODR)

Bit

Initial value

Slave Read/Write

Host Read/Write

ODR7

—

R/W

ODR6

—

R/W

ODR5

—

R/W

ODR4

—

R/W

ODR3

—

R/W

ODR0

—

R/W

ODR2

—

R/W

ODR1

—

R/W

ODRn (n = 1 to 4) is an 8-bit readable/writable register to the slave processor, and an 8-bit read-

only register to the host processor. The ODRn contents are output on the host data bus when HA0

is low,

CSn (n = 1 to 4) is low, and IOR is low.

The initial values of ODR after a reset and in standby mode are undetermined.

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