HD64F2149YV datasheet(624/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 18A Host Interface X-Bus Interface (XBS)

Rev. 3.00 Jan 18, 2006 page 596 of 1044

REJ09B0280-0300

detected, bit 1 of the data following the host command is output from the GA20 output pin. This

operation does not depend on firmware or interrupts, and is faster than the regular processing

using interrupts. Table 18A.6 lists the conditions that set and clear GA20 (P81). Figure 18A.2

shows the GA20 output in flowchart form. Table 18A.7 indicates the GA20 output signal values.

Table 18A.6 GA20 (P81) Set/Clear Timing

Pin Name

Setting Condition

Clearing Condition

GA20

(P81)

Rising edge of the host’s write signal

(

IOW) when bit 1 of the written data is 1

and the data follows an H'D1 host

command

Rising edge of the host’s write signal

(

IOW) when bit 1 of the written data is 0

and the data follows an H'D1 host

command

Also, when bit FGA20E in HICR is cleared

to 0

Start

Host write

H'D1 command

received?

Wait for next byte

Host write

Yes

Data byte?

Write bit 1 of data byte

to DR bit of P81/GA20

Yes

Figure 18A.2 GA20 Output Flowchart

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