HD64F2149YV datasheet(616/1075 Pages) RENESAS

Nome de Peças	HD64F2149YV

Descrição Electrónicos	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Section 18A Host Interface X-Bus Interface (XBS)

Rev. 3.00 Jan 18, 2006 page 588 of 1044

REJ09B0280-0300

18A.2.3 Host Interface Control Register (HICR)

• HICR

Bit

Initial value

Slave Read/Write

Host Read/Write

—

FGA20E

R/W

—

IBFIE2

R/W

—

IBFIE1

R/W

—

• HICR2

Bit

Initial value

Slave Read/Write

Host Read/Write

—

IBFIE4

R/W

—

IBFIE3

R/W

—

HICR is an 8-bit readable/writable register which controls host interface channel 1 and 2 interrupts

and the fast A20 gate function. HICR2 is an 8-bit readable/writable register which controls host

interface channel 3 and 4 interrupts. HICR and HICR2 are initialized to H'F8 by a reset and in

hardware standby mode.

Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.

HICR Bits 2 and 1—Input Data Register Full Interrupt Enable 2 and 1 (IBFIE2, IBFIE1)

HICR2 Bits 2 and 1—Input Data Register Full Interrupt Enable 4 and 3 (IBFIE4, IBFIE3)

These bits enable or disable the IBF1 to IBF4 interrupts to the internal CPU.

HD64F2149YV Folha de dados(PDF) 616 Page - Renesas Technology Corp