HD64F2149YV datasheet(619/1075 Pages) RENESAS

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Section 18A Host Interface X-Bus Interface (XBS)

Rev. 3.00 Jan 18, 2006 page 591 of 1044

REJ09B0280-0300

18A.2.6 Status Register (STR)

Bit

Initial value

Slave Read/Write

Host Read/Write

Note: * Only 0 can be written, to clear the flag.

DBU

R/W

DBU

R/W

DBU

R/W

DBU

R/W

OBF

R/(W)*

DBU

R/W

IBF

STRn (n = 1 to 4) is an 8-bit register that indicates status information during host interface

processing. Bits 3, 1, and 0 are read-only bits to both the host and the slave processors.

STR is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 to 4 and Bit 2—Defined by User (DBU): The user can use these bits as necessary.

Bit 3—Command/Data (C/

D): Receives the HA0 input when the host processor writes to IDR,

and indicates whether IDR contains data or a command.

Bit 3

Description

Contents of input data register (IDR) are data

(Initial value)

Contents of input data register (IDR) are a command

Bit 1—Input Buffer Full (IBF): Set to 1 when the host processor writes to IDR. This bit is an

internal interrupt source to the slave processor. IBF is cleared to 0 when the slave processor reads

IDR.

The IBF flag setting and clearing conditions are different when the fast A20 gate is used. For

details see table 18A.7.

Bit 1

IBF

Description

[Clearing condition]

When the slave processor reads IDR

(Initial value)

[Setting condition]

When the host processor writes to IDR

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