Os motores de busca de Datasheet de Componentes eletrônicos
  Portuguese  ▼
ALLDATASHEETPT.COM

X  

HD64F2149YV Folha de dados(PDF) 617 Page - Renesas Technology Corp

Nome de Peças HD64F2149YV
Descrição Electrónicos  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Fabricante Electrônico  RENESAS [Renesas Technology Corp]
Página de início  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV Folha de dados(HTML) 617 Page - Renesas Technology Corp

Back Button HD64F2149YV Datasheet HTML 613Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 614Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 615Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 616Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 617Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 618Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 619Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 620Page - Renesas Technology Corp HD64F2149YV Datasheet HTML 621Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 617 / 1075 page
background image
Section 18A Host Interface X-Bus Interface (XBS)
Rev. 3.00 Jan 18, 2006 page 589 of 1044
REJ09B0280-0300
HICR2
Bit 2
HICR2
Bit 1
HICR
Bit 2
HICR
Bit 1
IBFIE4
IBFIE3
IBFIE2
IBFIE1
Description
——
—
0
Input data register (IDR1) reception completed interrupt
request disabled
(Initial value)
——
—
1
Input data register (IDR1) reception completed interrupt
request enabled
——
0
—
Input data register (IDR2) reception completed interrupt
request disabled
(Initial value)
——
1
—
Input data register (IDR2) reception completed interrupt
request enabled
—
0
——
Input data register (IDR3) reception completed interrupt
request disabled
(Initial value)
—
1
——
Input data register (IDR3) reception completed interrupt
request enabled
0
——
—
Input data register (IDR4) reception completed interrupt
request disabled
(Initial value)
1
——
—
Input data register (IDR4) reception completed interrupt
request enabled
HICR Bit 0—Fast A20 Gate Function Enable (FGA20E): Enables or disables the fast A20 gate
function. When the fast A20 gate is disabled, the normal A20 gate can be implemented byte
firmware operation of the P81 output.
When the host interface (HIF:XBS) fast A20 gate function is enabled, the DDR bit for P81 must
be set to 1. Therefore, the state of the P81/GA20 pin cannot be monitored by reading the DR bit
for P81.
A fast A20 gate function is also provided in the HIF:LPC. The state of the P81/GA20 pin can be
monitored by reading the HIF:LPC’s GA20 bit.
HICR
Bit 0
P8DDR
Bit 1
FGA20E
P81DDR
Description
0
0
HIF:XBS fast A20 gate function disabled
(Initial value)
1
HIF:XBS fast A20 gate function disabled
1
0
Setting prohibited
1
HIF:XBS fast A20 gate function enabled



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


Folha de dados Download

Go To PDF Page


Ligação URL



ALLDATASHEET é útil para você?  [ DONATE ] 

Sobre Alldatasheet   |   Publicidade   |   Contato conosco   |   Privacy Policy   |   Link para a ficha técnica    |   roca de Link   |   Lista de Fabricantes
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com