HD64F2149YV datasheet(614/1075 Pages) RENESAS

614 / 1075 page

Section 18A Host Interface X-Bus Interface (XBS)

Rev. 3.00 Jan 18, 2006 page 586 of 1044

REJ09B0280-0300

Bit 1

HIE

Description

HIF:XBS register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU access is

disabled

(Initial value)

HIF:XBS register (HICR, IDR1, ODR1, STR1, IDR2, ODR2, STR2), CPU access is

enabled

18A.2.2 System Control Register 2 (SYSCR2)

Bit

654

321

KWUL1

KWUL0

P6PUE

—

SDE

CS4E

CS3E

HI12E

Initial value

000

Read/Write

R/W

—

R/W

SYSCR2 is an 8-bit readable/writable register which controls the chip operations. Host interface

functions are enabled or disabled by the HI12E bit in SYSCR2. The number of channels that can

be used can be extended to a maximum of four by means of the CS3E bit and CS4E bit. SYSCR2

is initialized to H'00 by a reset and in hardware standby mode.

Bits 7 and 6—Key Wakeup Level 1 and 0 (KWUL1, KWUL0): The port 6 input level can be

set and changed by software. For details see section 8, I/O Ports.

Bit 5—Port 6 MOS Input Pull-Up Extra (P6PUE): Controls and selects the current

specification for the port 6 MOS input pull-up function connected by means of KMPCR settings.

For details see section 8, I/O Ports.

Bit 4—Reserved: Do not write 1 to this bit.

Bit 3—Shutdown Enable (SDE): Enables or disables the host interface pin shutdown function.

When this function is enabled, host interface pin functions can be halted, and the pins placed in the

high-impedance state, according to the state of the HIFSD pin.

Bit 3

SDE

Description

Host interface pin shutdown function disabled

(Initial value)

Host interface pin shutdown function enabled

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