HD64F2149YV datasheet(613/1075 Pages) RENESAS

613 / 1075 page

Section 18A Host Interface X-Bus Interface (XBS)

Rev. 3.00 Jan 18, 2006 page 585 of 1044

REJ09B0280-0300

18A.2 Register Descriptions

18A.2.1 System Control Register (SYSCR)

Bit

Initial value

Read/Write

CS2E

R/W

IOSE

R/W

INTM1

INTM0

R/W

XRST

RAME

R/W

NMIEG

R/W

HIE

R/W

SYSCR is an 8-bit readable/writable register which controls the chip operations. Of the host

interface registers, HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2 can only be accessed

when the HIE bit is set to 1. HICR2, IDR3, ODR3, STR3, IDR4, ODR4, and STR4 can be

accessed regardless of the setting of the HIE bit. The host interface

CS2 and ECS2 pins are

controlled by the CS2E bit in SYSCR and the FGA20E bit in HICR. See section 3.2.2, System

Control Register (SYSCR), and section 5.2.1, System Control Register (SYSCR), for information

on other SYSCR bits. SYSCR is initialized to H'09 by a reset and in hardware standby mode.

Bit 7—CS2 Enable Bit (CS2E): Used together with the FGA20E bit in HICR to select the pin

that performs the

CS2 pin function when the HI12E bit is set to 1.

SYSCR

Bit 7

HICR

Bit 0

CS2E

FGA20E

Description

CS2 pin function halted (CS2 fixed high internally)

(Initial value)

CS2 pin function selected for P81/CS2 pin

CS2 pin function selected for P90/ECS2 pin

Bit 1—Host Interface Enable Bit (HIE): Enables or disables CPU access to the host interface

registers, keyboard matrix interrupt mask register (KMIMR), keyboard matrix interrupt mask

host interface registers (HICR, IDR1, ODR1, STR1, IDR2, ODR2, and STR2) can be accessed.

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