HD64F2149YV datasheet(611/1075 Pages) RENESAS

611 / 1075 page

Section 18A Host Interface X-Bus Interface (XBS)

Rev. 3.00 Jan 18, 2006 page 583 of 1044

REJ09B0280-0300

18A.1.3 Input and Output Pins

Table 18A.1 lists the input and output pins of the HIF:XBS module.

Table 18A.1 Host Interface Input/Output Pins

Name

Abbreviation

Port

I/O

Function

I/O read

IOR

P93

Input

Host interface read signal

I/O write

IOW

P94

Input

Host interface write signal

Chip select 1

CS1

P95

Input

Host interface chip select signal for IDR1,

ODR1, STR1

Chip select 2*

CS2

P81

Input

Host interface chip select signal for IDR2,

ECS2

P90

ODR2, STR2

Chip select 3

CS3

PB2

Input

Host interface chip select signal for IDR3,

ODR3, STR3

Chip select 4

CS4

PB3

Input

Host interface chip select signal for IDR4,

ODR4, STR4

Command/data

HA0

P80

Input

Host interface address select signal.

In host read access, this signal selects the

status registers (STR1 to STR4) or data

registers (ODR1 to ODR4). In host write

access to the data registers (IDR1 to IDR3,

and IDTR4), this signal indicates whether

the host is writing a command or data.

Data bus

HDB7 to HDB0 P37 to

P30

I/O

Host interface data bus

Host interrupt 1

HIRQ1

P44

Output

Interrupt output 1 to host

Host interrupt 11

HIRQ11

P43

Output

Interrupt output 11 to host

Host interrupt 12

HIRQ12

P45

Output

Interrupt output 12 to host

Host interrupt 3

HIRQ3

PB0

Output

Interrupt output 3 to host

Host interrupt 4

HIRQ4

PB1

Output

Interrupt output 4 to host

Gate A20

GA20

P81

Output

A20 gate control signal output

HIF shutdown

HIFSD

P82

Input

Host interface shutdown control signal

Note:

Selection of

CS2 or ECS2 is by means of the CS2E bit in STCR and the FGA20E bit in

HICR. HIF:XBS channel 2 and the

CS2 pin can be used when CS2E = 1. When CS2E =

CS2 is used when FGA20E =0, and ECS2 is used when FGA20E = 1. In this manual,

both are referred to as

CS2.

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