HD64F2149YV datasheet(609/1075 Pages) RENESAS

609 / 1075 page

Section 18A Host Interface X-Bus Interface (XBS)

Rev. 3.00 Jan 18, 2006 page 581 of 1044

REJ09B0280-0300

Section 18A Host Interface

X-Bus Interface (XBS)

18A.1 Overview

The H8S/2169 or H8S/2149 has an on-chip host interface (HIF) that enables connection to the ISA

bus (X-BUS) widely used as the internal bus in personal computers. In addition, the H8S/2169 or

H8S/2149 has an on-chip LPC interface, a new host interface replacing the ISA bus. In the

following text, these two host interfaces (HIFs) are referred to as XBS and LPC, respectively.

The HIF:XBS provides a four-channel parallel interface between the chip’s internal CPU and a

host processor.

The HIF:XBS is available only when bit HI12E is set to 1 in SYSCR2 in single-chip mode. Do not

set bit HI12E to 1 when using the HIF:LPC function.

18A.1.1 Features

The features of the HIF:XBS are summarized below.

The HIF:XBS consists of 8-byte data registers, 4-byte status registers, a 2-byte control register,

fast A20 gate logic, and a host interrupt request circuit. Communication is carried out via seven

control signals from the host processor (

CS1, CS2 or ECS2, CS3, CS4, HA0, IOR, and IOW), six

output signals to the host processor (GA20, HIRQ1, HIRQ11, HIRQ12, HIRQ3, and HIRQ4), and

an 8-bit bidirectional command/data bus (HDB7 to HDB0). The

CS1, CS2 (or ECS2), CS3 and

CS4 signals select one of the four interface channels.

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