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GD32H757VMT7 Folha de dados(PDF) 131 Page - GigaDevice Semiconductor (Beijing) Inc. |
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GD32H757VMT7 Folha de dados(HTML) 131 Page - GigaDevice Semiconductor (Beijing) Inc. |
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131 / 151 page ![]() GD32H757xx Datasheet 130 Symbol Parameter Conditions Min Typ Max Unit tSCK(H) SCK clock high time Fplckx = 300 MHz 13.3 — — ns tSCK(L) SCK clock low time Fplckx = 300 MHz 13.3 — — ns (1) Value guaranteed by design, not 100% tested in production. Table 4-64. USART characteristics in Smartcard mode(1) Symbol Parameter Conditions Min Typ Max Unit fSCK SCK clock frequency Fplckx = 300 MHz — — 150 MHz tSCK(H) SCK clock high time Fplckx = 300 MHz 3.33 — — ns tSCK(L) SCK clock low time Fplckx = 300 MHz 3.33 — — ns (1) Value guaranteed by design, not 100% tested in production. 4.30. SDIO characteristics Table 4-65. SDIO characteristics(1)(2) Symbol Parameter Conditions Min Typ Max Unit fPP(3) Clock frequency in data transfer mode — 0 — 120 MHz tW(CKL) (3) Clock low time fpp = 52 MHz — 9.63 — ns tW(CKH) (3) Clock high time fpp = 52 MHz — 9.58 — ns CMD, D inputs (referenced to CK) in MMC and SD HS mode tISU(4) Input setup time HS — 3 — — ns tIH(4) Input hold time HS — 1 — — ns CMD, D outputs (referenced to CK) in MMC and SD HS mode tOV(3) Output valid time HS — — 5.5 6 ns tOH(3) Output hold time HS — 4 — — ns CMD, D inputs (referenced to CK) in SD default mode tISUD(4) Input setup time SD — 2 — — ns tIHD(4) Input hold time SD — 1 — — ns CMD, D outputs (referenced to CK) in SD default mode tOVD(3) Output valid default time SD — — 1 1 ns tOHD(3) Output hold default time SD — 0 — — ns (1) CLK timing is measured at 50% of VDD. (2) Capacitive load CL = 30 pF. (3) Value guaranteed by characterization, not 100% tested in production. (4) Value guaranteed by design, not 100% tested in production. 4.31. CAN characteristics Refer to Table 4-28. I/O static characteristics for more details on the input/output alternate function characteristics (CANTX and CANRX). |
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