GD32H757VMT7 datasheet(128/151 Pages) GIGADEVICE

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GD32H757xx Datasheet

127

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

frequency

DutyCKOUT

Output clock

frequency duty

cycle

—

twh(CKIN)

twl(CKIN)

Input clock high and

low time

SPI mode(SITYP[1:0] = 01),

External clock

mode(SPICKSS[1:0] = 0)

TCKIN / 2-

0.5

TCKIN /

—

tSU

Data input setup

time

SPI mode(SITYP[1:0] = 01),

External clock

mode(SPICKSS[1:0] = 0)

—

Data input hold time

SPI mode(SITYP[1:0] = 01),

External clock

mode(SPICKSS[1:0] = 0)

—

TManchester

Manchester data

period(recovered

clock period)

Manchester mode(SITYP[1:0] =

10 or 11), Internal clock

mode(SPICKSS[1:0] ≠ 0)

(CKOUT

DIV+1)*T

HPDFCLK

—

(2*CKOU

TDIV)*TH

PDFCLK

(1)

Value guaranteed by design, not 100% tested in production.

(2)

Output speed is set to OSPEEDRy[1:0] = 10

；Capacitive load C = 30 pF；Measurement points are done at

COMS levels: 0.5 * VDD.

4.27.

SAI characteristics

Table 4-61. SAI characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fMCK

SAI Main clock output

—

MHz

fCK

SAI clock frequency

Master

transmitter, 2.7 V ≤ VDD ≤ 3.6

—

Master transmitter, 1.71 V ≤ VDD ≤

3.6 V

—

Master receiver, 1.71 V ≤ VDD ≤ 3.6

—

Slave transmitter, 2.7 V ≤ VDD ≤ 3.6

—

47.5

Slave transmitter, 1.71 V ≤ VDD ≤ 3.6

—

41.5

Slave

receiver, 1.71 V ≤ VDD ≤ 3.6 V

—

(1)

Value guaranteed by design, not 100% tested in production.

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