GD32H757VMT7 datasheet(65/151 Pages) GIGADEVICE

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GD32H757xx Datasheet

detector (LVD).

The Clock Control Unit (CCTL) provides a range of oscillator and clock functions. These

include internal RC oscillator and external crystal oscillator, high speed and low speed two

types. Several prescalers allow the frequency configuration of the AXI, three AHB and four

APB

domains. The maximum frequency of the system clock can be up to 600 MHz. The

maximum frequency of the three AHB domains are 300 MHz. The maximum frequency of the

four APB domains including APB1 = APB3 = PAB4 is 150 MHz and APB2 is 300 MHz. See

Figure 2-5. GD32H757xx clock tree

for details on the clock tree.

The Reset Control Unit (RCU) controls three kinds of reset: system reset resets the processor

core and peripheral IP components except for the SW-DP controller and the Backup domain.

Power-on reset (POR) and power-down reset (PDR) are always active, and ensures proper

operation starting from 1.53V and down to 1.48V. The device remains in reset mode when

VDD is below a specified threshold

. The embedded low voltage detector (LVD) monitors the

power supply, compares it to the voltage threshold and generates an interrupt as a warning

message for leading the MCU into security.

Power supply schemes:



VDD range: 1.71V to 3.6V, external power supply for I/Os and the internal regulator.

Provided externally through VDD pins.



VSSA, VDDA range: 1.71V to 3.6V, external analog power supplies for ADC, reset blocks,

RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.



VBAT range: 1.71V to 3.6V, power supply for RTC, external clock 32 KHz oscillator and

backup registers (through power switch) when VDD is not present.

3.4.

Boot modes

GD32H757xx supports four BOOT modes, including:



USER BOOT



SECURITY BOOT



SYSTEM BOOT



SRAM BOOT

At startup, the boot memory space is selected by the BOOT pin and BOOT_ADDR0/1 in Boot

address

, allowing to program any boot memory address from 0x0000 0000 to to 0x9000 0000.

The boot loader is located in non-user System memory. It is used to reprogram the Flash

memory by using USART0 (PA9 and PA10), USART1 (PA2 and PA3), USART2 (PB10 and

PB11), USBHS0 (USBHS0_DP and USBHS0_DM) and SDIO0 (PC12, PD2, PB13, PC9,

PC10 and PC11) in device mode. It also can be used to transfer and update the Flash memory

code, the data and the vector table sections.

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