GD32H757VMT7 datasheet(70/151 Pages) GIGADEVICE

70 / 151 page

GD32H757xx Datasheet



Support independent single, 2, 4, 8, 16, 32, 64, 128-beat incrementing burst source and

destination transfer.



Support three transfer modes:

–

Read from memory and write to memory (software triggered).

–

Read from peripheral and write to memory (or memory mapped peripherals).

–

Read from memory (or memory mapped peripherals) and write to peripheral.



Automatic pack / unpack of data to optimize bandwidth when the data width of the source

and destination are different.



34 hardware trigger sources, all channels can be connected to any hardware trigger

source.



Two FIFOs of 16 double word depth to maximize data bandwidth and bus utilization.

The master direct memory access (MDMA) controller provides a hardware method of

transferring data between peripherals and/or memory without intervention from the MCU,

thereby increasing system performance by off-loading the MCU from copying large amounts

of data and avoiding frequent interrupts to serve peripherals needing more data or having

available data. MDMA can be used in combination with a DMA controller (DMA0 or DMA1) to

provide up to 16 channels. Each channel request can be selected among any request source.

The built-in arbiter is used to handle priority among MDMA requests.

3.16.

DMA request multiplexer (DMAMUX)

 16 channels for DMAMUX

request multiplexer.



8 channels for DMAMUX request generator.



Support 36 trigger inputs and 29 synchronization inputs.

DMAMUX is a transmission scheduler for DMA requests. The DMAMUX request multiplexer

is used for routing a DMA request line between the peripherals / generated DMA request

(from the DMAMUX request generator) and the DMA controller. Each DMAMUX request

multiplexer channel selects a unique DMA request line, unconditionally or synchronously with

events from its DMAMUX synchronization inputs. The DMA request is pending until it is

served by the DMA controller which generates a DMA acknowledge signal (the DMA request

signal is de-asserted).

3.17.

Analog to digital converter (ADC)



14-bit ADC0 and ADC1 conversion rate is up to 4 MSPS.



12-bit ADC2 conversion rate is up to 5.3 MSPS.



14-bit,12-bit, 10-bit, 8-bit configurable resolution for ADC0 and ADC1.



12-bit, 10-bit, 8-bit or 6-bit configurable resolution for ADC2.



In ADC0 and ADC1, Oversampling ratio arbitrarily adjustable from 2x to 1024X.



ADC2, Oversampling ratio arbitrarily adjustable from 2x to 256X.



ADC0 and ADC1 supply requirements: 1.8V to 3.6V, and typical power supply voltage is

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