GD32H757VMT7 datasheet(124/151 Pages) GIGADEVICE

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GD32H757xx Datasheet

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Figure 4-7. I2C bus timing diagram

70%

30%

tF(SDA)

30%

70%

tR(SDA)

tH(STA)

tSCL(L)

tSCL(H)

tR(SCL)

tF(SCL)

tH(SDA)

tSU(SDA)

SDA

SCL

tBUFF

tSU(STA)

tSU(STO)

70%

30%

70%

Table 4-56. I2C analog filter delay characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

tAF

Analog filter delay time

—

130

(1)

Value guaranteed by design, not 100% tested in production.

4.23.

SPI characteristics

Table 4-57. Standard SPI characteristics(1)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fSCK

SCK clock frequency

—

125

MHz

tSCK(H)

SCK clock high time

—

tSCK(L)

SCK clock low time

—

SPI master mode

tV(MO)

Data output valid time

—

tH(MO)

Data output hold time

—

tSU(MI)

Data input setup time

—

tH(MI)

Data input hold time

—

SPI slave mode

tSU(NSS)

NSS enable setup time

—

tH(NSS)

NSS enable hold time

—

tA(SO)

Data output access time

—

tDIS(SO)

Data output disable time

—

tV(SO)

Data output valid time

—

tH(SO)

Data output hold time

—

tSU(SI)

Data input setup time

—

tH(SI)

Data input hold time

—

(1)

Value guaranteed by characterization, not 100% tested in production.

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