ADMV1455BBCZ-R7 datasheet(82/141 Pages) AD

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Data Sheet

ADMV1455

THEORY OF OPERATION

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DSA4

The DSA directly after the IF BPF in the IF signal chains is DSA4.

This attenuator offers 16 states, 0dB to 15dB, with steps of 1dB.

The attenuation is proportional to the value programmed. When

using the bypass registers (Register 0x28A set to 1), use Register

0x28C, Bits[7:4], to set the DSA4 state. When not using the bypass

registers (Register 0x28A set to 0), use Register 0x601, Bits[7:4], to

set the DSA4 state.

DSA5

The DSA directly after DSA4 in the IF signal chains is DSA5.

This attenuator offers 16 states, 0dB to 15dB, with steps of 1dB.

The attenuation is proportional to the value programmed. When

using the bypass registers (Register 0x28A set to 1), use Register

0x28D, Bits[3:0], to set the DSA5 state. When not using the bypass

registers (Register 0x28A set to 0), use Register 0x602, Bits[3:0] to

set the DSA5 state.

TOTAL GAIN CONTROL

Table 25 is the typical total available gain (attenuation) control for

each configuration that can be implemented with the ADMV1455.

Table 25. Typical Total Available Gain (Attenuation) for Each Configuration

Configuration

Available Attenuation (dB)

Input

Output

LNA (RF_IN)

I/Q baseband

DSA1 (DSA_IN)

I/Q baseband

RF GAIN POLICY

The RF gain (attenuation) policy to achieve the best noise figure

performance is to keep all DSAs at their maximum gain state.

When it is necessary to reduce the gain and the noise figure is

prioritized, it is then best to set the attenuation in reverse order.

For IF mode, start by introducing attenuation in DSA5, followed by

DSA4, DSA3, DSA2, and then DSA1. For I/Q baseband mode, it

start by introducing attenuation in DSA3, DSA2, and then DSA1.

To optimize input P1dB and input IP3 performance, set the attenua-

tion in normal order. For IF mode, start by introducing attenuation in

DSA1, followed by DSA2, DSA3, DSA4, and then DSA5. Note that

this gain policy significantly degrades noise figure performance.

To balance input P1dB, input IP3, and noise figure, set attenuation

in DSA4 and then DSA5. This gain improves P1dB and IIP3 while

having minimal impact on noise figure.

AUTOMATIC ADC CONFIGURATION

The ADMV1455 includes an on-chip, automatic ADC that can

continuously capture the power detector and temperature sensor

values. The values can then be read back using the SPI via

The ADC also contains averaging that can be configured using

determined by 2 raised to the power of the value in Register 0x055.

The recommended value is 27, or 128 averages. The ADC capture

time is inversely proportional to the number of averages.

To set up the automatic ADC configuration, take the following steps:

1. Set Register 0x107, Bit 7 and Bit 5 to value 0, which powers up

the temperature sensor and the ADC.

2. Set Register 0x178 to the value desired, DETEC-

TOR_RES_CTRL, typically 7.

3. Set Register 0x043 to 0x00 to disable the ADC_CLK.

4. Set Register 0x051 to 0x00 to set the ADC for automatic mode.

5. Set Register 0x055 to 0x07 to set ADC_FILTER_TAPS averag-

ing to 27.

6. Set Register 0x052 to 0x21 for reading of both the pow-

er detector and temperature sensor, as well as set the

ADC_CLK_FREQ to 3.5MHz.

7. Set Register 0x05F to 0x00 to ensure that the digital filter is not

held in reset.

8. Set Register 0x043 to 0x01 to enable the ADC_CLK.

Perform read backs of the following registers for the power detector

and temperature sensor values:

1. Read Register 0x041 for the power detector value.

2. Read Register 0x040 for the temperature sensor value.

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