ADMV1455BBCZ-R7 datasheet(67/141 Pages) AD

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Data Sheet

ADMV1455

THEORY OF OPERATION

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Rev. 0 | 67 of 141

TIMING DIAGRAMS OVERVIEW

The timing diagrams shown in Figure 167, Figure 168, Figure 169,

and Figure 170 help with visualizing the various programming and

power sequences of operation for the ADMV1455. These timing

diagrams utilize the timing specifications detailed in Table 8.

Contained within this guidance are limitations to prevent possible

damage to the ADMV1455, such as keeping the digital inputs low

during power up and removing the digital inputs before or at the

same time as power down. Additionally, the timing diagrams contain

best practices for operation, such as programming the necessary

SPI instructions prior to enabling the RF portions of the chip using

the CEN input.

See the Power-Up and Apply the Digital Inputs section, the Initial-

ization SPI Instructions section, the Chip Enable and Operation

section, the Chip Disable and Reset section, and the Chip Disable

and Power-Down section for additional details regarding these

timing diagrams.

Power-Up and Apply the Digital Inputs

The power-up and initialization timing diagram (see Figure 167)

shows the power supplies rising by t1, starting from the start time,

tSTART. After the power supply voltages have been brought to

90% of their nominal values, valid digital inputs can be applied

after waiting a minimum time of t2 at tDIGITAL. To prevent possible

damage to the chip, do not apply digital inputs before tDIGITAL.

Generally, at tDIGITAL, the RST and CS inputs go high together. If

applicable, the CHIP_ADD0 and CHIP_ADD1 are also set at this

time in preparation for the SPI instructions. Wait a minimum of t3 to

allow the chip to reset before beginning the SPI instructions at the

initialization time, tINITIALIZE.

Figure 167. Power-Up and Initialization Timing Diagram

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