ADMV1455BBCZ-R7 datasheet(74/141 Pages) AD

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Data Sheet

ADMV1455

THEORY OF OPERATION

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Rev. 0 | 74 of 141

GENERAL-PURPOSE OUTPUTS

The ADMV1455 includes 11 genera- purpose outputs that can be

used to set logic levels of other components within a system, such

as standalone tunable filters or standalone DSAs. These outputs

support 1.8V logic levels and can be defined by either the SPI or by

the LUTs.

Before using any of the general-purpose outputs, it is necessary

to set the output enable bit to 1 for that output by using Register

0x780 and Register 0x781. The output state, logic high or logic low,

is then determined by the values programmed into Register 0x603

and Register 0x805. Refer to Table 20 table for more details.

Table 20. GPO Registers

Output

Output Enable

Output State

Bit

GPO_F0

0x780

0x805

GPO_F1

0x780

0x805

GPO_F2

0x780

0x805

GPO_F3

0x780

0x805

GPO_F4

0x780

0x805

GPO_F5

0x780

0x805

GPO_G0

0x780

0x603

GPO_G1

0x780

0x603

GPO_G2

0x781

0x603

GPO_G3

0x781

0x603

GPO_G4

0x781

0x603

RF CONNECTIONS

The RF connections of the ADMV1455 are considered DC-cou-

pled. If a DC voltage is present on the connections from other

components within the system, it is recommended to place DC

blocking capacitors in series with these pins. The DC blocking

capacitors must be selected based on the operating frequency of

the filter. Generally, a value greater than 100pF is sufficient to

minimize insertion loss at the lower frequencies of operation. At

higher frequencies of operation, it may be necessary to consider

the parasitic elements of the selected capacitor. Figure 173 shows

a general model of a capacitor with the parasitic elements. The

parasitic series inductance (LESL) is typically of most concern given

that its impedance can become dominant at frequencies of more

than 10GHz. The other parasitic elements, including the leakage

resistance (RL), dielectric absorption resistance (RDA), dielectric ab-

sorption capacitance (CDA), and electrical series resistance (RESR)

are less critical elements for consideration but are shown here for

completeness.

Figure 173. General Model of a Capacitor

LO SIGNAL CHAIN

The LO signal chain of the ADMV1455 accepts an input signal

from the LO ball. The LO input signal is buffered with an amplifier,

doubled using a 2× multiplier, before being fed into tunable filters,

a wideband 90° hybrid, and two adjustable phase shifters. Figure

174 shows the LO signal chain. The LO signal chain is specified to

operate with input frequencies from 8.85GHz to 27.5GHz.

Figure 174. LO Chain Diagram

For input frequencies less than 25GHz, the specified input pow-

er levels are from −7dBm to −3dBm. Functional, but degraded

performance, is possible with input power levels from −10dBm to

−7dBm and from −3dBm to 0dBm.

For input frequencies greater than or equal to 25GHz, the specified

input levels are from −3dBm to 0dBm. Functional, but degraded

performance, is possible with input power levels from −10dBm to

−3dBm.

Minimize the harmonic content of the LO input signal to prevent

unwanted spurious mixer products. It is recommended to keep all

LO input harmonic signals −40dBc less than the fundamental LO

signal.

To help reduce spurious mixer products, the LO tunable filters are

used to optimize any LO harmonic content that may be present

after the 2× multiplier. Refer to the LO Tunable Filters section for

more recommendations on setting these tunable filters.

The wideband 90° hybrid and adjustable phase shifters generate

the necessary mixer LO signals, 2×LO_I and 2×LO_Q. The mixer

LO signals operate from 17.7GHz to 55GHz. The adjustable phase

shifters allow for trimming the quadrature phase of the mixer LO

signals, which can be used in conjunction with the fine adjust

attenuators, DSAI and DSAQ, to optimize the image rejection

capability of the ADMV1455. Refer to Image Rejection Optimization

section for more information on how to perform this optimization.

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