BQ25708 datasheet(82/94 Pages) TI2

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12 Layout

12.1 Layout Guidelines

Proper layout of the components to minimize high frequency current path loop (see Section 12.2) is important

to prevent electrical and magnetic field radiation and high frequency resonant problems. Here is a PCB layout

priority list for proper layout.

Table 12-1. PCB Layout Guidelines

RULES

COMPONENTS

FUNCTION

IMPACT

GUIDELINES

PCB layer stack up

Thermal, efficiency,

signal integrity

Multi- layer PCB is suggested. Allocate at least one ground layer.

The BQ257XXEVM uses a 4-layer PCB (top layer, ground layer,

signal layer and bottom layer).

CBUS, RAC, Q1,

Input loop

High frequency

noise, ripple

VBUS capacitors, RAC, Q1 and Q2 form a small loop 1. It is best

to put them on the same side. Connect them with large copper to

reduce the parasitic resistance. Move part of CBUS to the other

side of PCB for high density design. After RAC before Q1 and

Q2 power stage recommend to put 10 nF + 1 nF (0402 package)

decoupling capacitors as close as possible to IC to decoupling

switching loop high frequency noise.

RAC, Q1, L1, Q4

Current path

Efficiency

The current path from VBUS to VSYS, through RAC, Q1, L1, Q4,

has low impedance. Pay attention to via resistance if they are not

on the same side. The number of vias can be estimated as 1 to

2A/via for a 10-mil via with 1 oz. copper thickness.

CSYS, Q3, Q4

Output loop

High frequency

noise, ripple

VSYS capacitors, Q3 and Q4 form a small loop 2. It is best to

put them on the same side. Connect them with large copper to

reduce the parasitic resistance. Move part of CSYS to the other

side of PCB for high density design.

QBAT, RSR

Current path

Efficiency, battery

voltage detection

Place QBAT and RSR near the battery terminal. The current path

from VBAT to VSYS, through RSRand QBAT, has low impedance.

Pay attention to via resistance if they are not on the same side.

The device detects the battery voltage through SRN near battery

terminal.

Q1, Q2, L1, Q3,

Power stage

Thermal, efficiency

Place Q1, Q2, L1, Q3 and Q4 next to each other. Allow

enough copper area for thermal dissipation. The copper area

is suggested to be 2x to 4x of the pad size. Multiple thermal

vias can be used to connect more copper layers together and

dissipate more heat.

RAC, RSR

Current sense

Regulation accuracy Use Kelvin-sensing technique for RAC and RSR current sense

resistors. Connect the current sense traces to the center of the

pads, and run current sense traces as differential pairs.

Small capacitors

IC bypass caps

Noise, jittering,

ripple

Place VBUS cap, VCC cap, REGN caps near IC.

BST capacitors

HS gate drive

High frequency

noise, ripple

Place HS MOSFET boost strap circuit capacitor close to IC and

on the same side of PCB board. Capacitors SW1/2 nodes are

recommended to use wide copper polygon to connect to power

stage and capacitors BST1/2 node are recommended to use at

least 8mil trace to connected to IC BST1/2 pins.

Ground partition

Measurement

accuracy, regulation

accuracy, jitters,

ripple

Separate analog ground(AGND) and power grounds(PGND) is

preferred. PGND should be used for all power stage related

ground net. AGND should be used for all sensing, compensation

and control network ground for example ACP/ACN/COMP1/

COMP2/CMPIN/CMPOUT/IADPT/IBAT/PSYS. Connect all

analog grounds to a dedicated low-impedance copper plane,

which is tied to the power ground underneath the IC exposed

pad. If possible, use dedicated COMP1, COMP2 AGND traces.

Connect analog ground and power ground together using power

pad as the single ground connection point.

BQ25713, BQ25713B

SLUSD83C – JUNE 2018 – REVISED MAY 2023

www.ti.com

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